AT32UC3C064C

Manufacturer Part NumberAT32UC3C064C
ManufacturerAtmel Corporation
AT32UC3C064C datasheets

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Specifications of AT32UC3C064C

Flash (kbytes)64 KbytesPin Count144
Max. Operating Frequency66 MHzCpu32-bit AVR
Hardware Qtouch AcquisitionNoMax I/o Pins123
Ext Interrupts144Usb Transceiver1
Quadrature Decoder Channels2Usb SpeedFull Speed
Usb InterfaceDevice + OTGSpi7
Twi (i2c)3Uart5
Can2Lin5
Ssc1Ethernet1
Graphic LcdNoVideo DecoderNo
Camera InterfaceNoAdc Channels16
Adc Resolution (bits)12Adc Speed (ksps)2000
Analog Comparators4Resistive Touch ScreenNo
Dac Channels4Dac Resolution (bits)12
Temp. SensorNoCrypto EngineNo
Sram (kbytes)20Self Program MemoryYES
External Bus Interface1Dram Memorysdram
Nand InterfaceNoPicopowerNo
Temp. Range (deg C)-40 to 85I/o Supply Class3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)3.0 to 3.6 or 4.5 to 5.5FpuYes
Mpu / MmuYes / NoTimers6
Output Compare Channels22Input Capture Channels12
Pwm Channels2032khz RtcYes
Calibrated Rc OscillatorYes  
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Page 20/377

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MMUCR - MMU Control Register
Used to control the MMU and the TLB. The contents and functionality of the register is described
in detail in
TLBARLO / TLBARHI - MMU TLB Accessed Register Low / High
Contains the Accessed bits for the TLB. The contents and functionality of the register is
described in detail in
PCCNT - Performance Clock Counter
Clock cycle counter for performance counters. The contents and functionality of the register is
described in detail in
PCNT0 / PCNT1 - Performance Counter 0 / 1
Counts the events specified by the Performance Counter Control Register. The contents and
functionality of the register is described in detail in
57.
PCCR - Performance Counter Control Register
Controls and configures the setup of the performance counters. The contents and functionality
of the register is described in detail in
BEAR - Bus Error Address Register
Physical address that caused a Data Bus Error. This register is Read Only. Writes are allowed,
but are ignored.
MPUARn - MPU Address Register n
Registers that define the base address and size of the protection regions. Refer to
“Memory Protection Unit” on page 51
MPUPSRn - MPU Privilege Select Register n
Registers that define which privilege register set to use for the different subregions in each pro-
tection region. Refer to
MPUCRA / MPUCRB - MPU Cacheable Register A / B
Registers that define if the different protection regions are cacheable. Refer to
ory Protection Unit” on page 51
MPUBRA / MPUBRB - MPU Bufferable Register A / B
Registers that define if the different protection regions are bufferable. Refer to
ory Protection Unit” on page 51
MPUAPRA / MPUAPRB - MPU Access Permission Register A / B
Registers that define the access permissions for the different protection regions. Refer to
tion 6. “Memory Protection Unit” on page 51
MPUCR - MPU Control Register
Register that control the operation of the MPU. Refer to
page 51
AVR32
20
Section 5. “Memory Management Unit” on page
Section 5. “Memory Management Unit” on page
Section 7. “Performance counters” on page
Section 7. “Performance counters” on page
for details.
Section 6. “Memory Protection Unit” on page 51
for details.
for details.
for details.
35.
35.
57.
Section 7. “Performance counters” on page
for details.
Section 6. “Mem-
Section 6. “Mem-
for details.
Section 6. “Memory Protection Unit” on
57.
Section 6.
Sec-
32000D–04/2011