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AT32UC3C064C
AT32UC3C064C | |
|---|---|
| Manufacturer Part Number | AT32UC3C064C |
| Manufacturer | Atmel Corporation |
| AT32UC3C064C datasheets |
|
Availability: In stock
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Specifications of AT32UC3C064C | |||
|---|---|---|---|
| Flash (kbytes) | 64 Kbytes | Pin Count | 144 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| Hardware Qtouch Acquisition | No | Max I/o Pins | 123 |
| Ext Interrupts | 144 | Usb Transceiver | 1 |
| Quadrature Decoder Channels | 2 | Usb Speed | Full Speed |
| Usb Interface | Device + OTG | Spi | 7 |
| Twi (i2c) | 3 | Uart | 5 |
| Can | 2 | Lin | 5 |
| Ssc | 1 | Ethernet | 1 |
| Graphic Lcd | No | Video Decoder | No |
| Camera Interface | No | Adc Channels | 16 |
| Adc Resolution (bits) | 12 | Adc Speed (ksps) | 2000 |
| Analog Comparators | 4 | Resistive Touch Screen | No |
| Dac Channels | 4 | Dac Resolution (bits) | 12 |
| Temp. Sensor | No | Crypto Engine | No |
| Sram (kbytes) | 20 | Self Program Memory | YES |
| External Bus Interface | 1 | Dram Memory | sdram |
| Nand Interface | No | Picopower | No |
| Temp. Range (deg C) | -40 to 85 | I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 |
| Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 | Fpu | Yes |
| Mpu / Mmu | Yes / No | Timers | 6 |
| Output Compare Channels | 22 | Input Capture Channels | 12 |
| Pwm Channels | 20 | 32khz Rtc | Yes |
| Calibrated Rc Oscillator | Yes | ||
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3C0128C PDF datasheet #3AT32UC3C0128C PDF datasheet #4
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PrevNext
SS_STATUS - Secure State Status Register
Register that can be used to pass status or other information from the secure state to the nonse-
cure state. Refer to
SS_ADRF, SS_ADRR, SS_ADR0, SS_ADR1 - Secure State Address Registers
Registers used to partition memories into a secure and a nonsecure section. Refer to
“Secure state” on page 31
SS_SP_SYS, SS_SP_APP - Secure State SP_SYS and SP_APP Registers
Read-only registers containing the SP_SYS and SP_APP values. Refer to
state” on page 31
SS_RAR, SS_RSR - Secure State Return Address and Return Status Registers
Contains the address and status register of the sscall instruction that called secure state. Also
used when returning to nonsecure state with the retss instruction. Refer to
state” on page 31
2.11.1
Configuration Registers
Configuration registers are used to inform applications and operating systems about the setup
and configuration of the processor on which it is running, see
implements the following read-only configuration registers.
Figure 2-8.
CONFIG0
31
CONFIG1
31
Table 2-8 on page 21
Table 2-8.
Name
Processor ID
RESERVED
Processor revision
32000D–04/2011
Section 4. “Secure state” on page 31
for details.
for details.
for details.
Configuration Registers
24
23
20
19
Processor
Processor ID
-
Revision
26
25
20 19
IMMU SZ
DMMU SZ
shows the CONFIG0 fields.
CONFIG0 Fields
Bit
Description
Specifies the type of processor. This allows the application to
31:24
distinguish between different processor implementations.
23:20
Reserved for future use.
19:16
Specifies the revision of the processor implementation.
for details.
Figure 2-8 on page
16 15
13 12
10
9
7 6
AT
AR
MMUT
16
15
13
12
10 9
ISET
ILSZ
IASS
DSET
AVR32
Section 4.
Section 4. “Secure
Section 4. “Secure
21. The AVR32
5
4
3 2
1
0
F
J
P O
S
D R
6 5
3
2
0
DLSZ
DASS
21
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