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AT32UC3C1128C
AT32UC3C1128C | |
|---|---|
| Manufacturer Part Number | AT32UC3C1128C |
| Manufacturer | Atmel Corporation |
| AT32UC3C1128C datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of AT32UC3C1128C | |||
|---|---|---|---|
| Flash (kbytes) | 128 Kbytes | Pin Count | 100 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| Hardware Qtouch Acquisition | No | Max I/o Pins | 81 |
| Ext Interrupts | 100 | Usb Transceiver | 1 |
| Quadrature Decoder Channels | 2 | Usb Speed | Full Speed |
| Usb Interface | Device + OTG | Spi | 7 |
| Twi (i2c) | 3 | Uart | 5 |
| Can | 2 | Lin | 5 |
| Ssc | 1 | Ethernet | 1 |
| Graphic Lcd | No | Video Decoder | No |
| Camera Interface | No | Adc Channels | 16 |
| Adc Resolution (bits) | 12 | Adc Speed (ksps) | 2000 |
| Analog Comparators | 4 | Resistive Touch Screen | No |
| Dac Channels | 4 | Dac Resolution (bits) | 12 |
| Temp. Sensor | No | Crypto Engine | No |
| Sram (kbytes) | 36 | Self Program Memory | YES |
| Dram Memory | No | Nand Interface | No |
| Picopower | No | Temp. Range (deg C) | -40 to 85 |
| I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 | Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 |
| Fpu | Yes | Mpu / Mmu | Yes / No |
| Timers | 6 | Output Compare Channels | 22 |
| Input Capture Channels | 12 | Pwm Channels | 19 |
| 32khz Rtc | Yes | Calibrated Rc Oscillator | Yes |
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3C0128C PDF datasheet #3AT32UC3C0128C PDF datasheet #4
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PrevNext
Table 9-10.
Load/Store Operations (Continued)
C
Rp++, Rs
C
--Rp, Rs
st.b
C
Rp[disp], Rs
E
Rp[disp], Rs
E
Rb[Ri<<sa], Rs
st.b{cond4}
E
Rp[disp], Rs
C
Rp++, Rs
C
--Rp, Rs
st.d
C
Rp, Rs
E
Rp[disp], Rs
E
Rb[Ri<<sa], Rs
C
Rp++, Rs
C
--Rp, Rs
st.h
C
Rp[disp], Rs
E
Rp[disp], Rs
E
Rb[Ri<<sa], Rs
st.h{cond4}
E
Rp[disp], Rs
C
Rp++, Rs
C
--Rp, Rs
st.w
C
Rp[disp], Rs
E
Rp[disp], Rs
E
Rb[Ri<<sa], Rs
st.w{cond4}
E
Rp[disp], Rs
stcond
C
Rp[disp], Rs
stdsp
C
SP[disp], Rs
Rp[disp], Rx:<part>,
E
Ry:<part>
sthh.w
Rb[Ri<<sa],
E
Rx:<part>, Ry:<part>
AVR32
116
Store with post-increment.
Store with pre-decrement.
Store byte with displacement.
Indexed Store byte.
Store byte with displacement if condition
satisfied.
Store with post-increment.
Store with pre-decrement.
Store doubleword
Store double with displacement
Indexed Store double.
Store with post-increment.
Store with pre-decrement.
Store halfword with displacement.
Indexed Store halfword.
Store halfword with displacement if
condition satisfied.
Store with post-increment.
Store with pre-decrement.
Store word with displacement.
Indexed Store word.
Store word with displacement if condition
satisfied.
Conditional store with displacement.
Store with displacement from SP.
Combine halfwords to word and store with
displacement.
Combine halfwords to word and store
indexed.
*(Rp++) ← Rs[7:0]
1
*(--Rp) ← Rs[7:0]
1
*(Rp+ZE(disp3)) ← Rs[7:0]
1
*(Rp+SE(disp16)) ← Rs[7:0]
1
*(Rb+(Ri << sa2)) ← Rs[7:0]
1
if {cond4}
2
*(Rp+SE(disp9)) ← Rs[7:0]
*(Rp++) ← (Rs+1:Rs)
1
*(--Rp) ← (Rs+1:Rs)
1
*(Rp) ← (Rs+1:Rs)
1
*(Rp+SE(disp16)) ← (Rs+1:Rs)
1
*(Rb+(Ri << sa2)) ← (Rs+1:Rs)
1
*(Rp++) ← Rs[15:0]
1
*(--Rp) ← Rs[15:0]
1
*(Rp+(ZE(disp3)<<1)) ← Rs[15:0]
1
*(Rp+(SE(disp16))) ← Rs[15:0]
1
*(Rb+(Ri << sa2)) ← Rs[15:0]
1
if {cond4}
2
*(Rp+SE(disp9<<1)) ← Rs[15:0]
*(Rp++) ← Rs
1
*(--Rp) ← Rs
1
*(Rp+(ZE(disp4)<<2)) ← Rs
1
*(Rp+(SE(disp16))) ← Rs
1
*(Rb+(Ri << sa2)) ← Rs
1
if {cond4}
2
*(Rp+ZE(disp9<<2)) ← Rs
SREG[Z] ← SREG[L]
if (SREG[L])
1
*(Rp+(SE(disp16))) ← Rs
*( (SP && 0xFFFF_FFFC)
1
+(ZE(disp7)<<2)) ← Rs
*(Rp+(ZE(disp8)<<2)) ←
1
{Rx:<part>, Ry:<part>}
*(Rb+(Ri << sa2)) ← {Rx:<part>,
1
Ry:<part>}
32000D–04/2011
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