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AT32UC3C1128C
AT32UC3C1128C | |
|---|---|
| Manufacturer Part Number | AT32UC3C1128C |
| Manufacturer | Atmel Corporation |
| AT32UC3C1128C datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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Specifications of AT32UC3C1128C | |||
|---|---|---|---|
| Flash (kbytes) | 128 Kbytes | Pin Count | 100 |
| Max. Operating Frequency | 66 MHz | Cpu | 32-bit AVR |
| Hardware Qtouch Acquisition | No | Max I/o Pins | 81 |
| Ext Interrupts | 100 | Usb Transceiver | 1 |
| Quadrature Decoder Channels | 2 | Usb Speed | Full Speed |
| Usb Interface | Device + OTG | Spi | 7 |
| Twi (i2c) | 3 | Uart | 5 |
| Can | 2 | Lin | 5 |
| Ssc | 1 | Ethernet | 1 |
| Graphic Lcd | No | Video Decoder | No |
| Camera Interface | No | Adc Channels | 16 |
| Adc Resolution (bits) | 12 | Adc Speed (ksps) | 2000 |
| Analog Comparators | 4 | Resistive Touch Screen | No |
| Dac Channels | 4 | Dac Resolution (bits) | 12 |
| Temp. Sensor | No | Crypto Engine | No |
| Sram (kbytes) | 36 | Self Program Memory | YES |
| Dram Memory | No | Nand Interface | No |
| Picopower | No | Temp. Range (deg C) | -40 to 85 |
| I/o Supply Class | 3.0 to 3.6 or 4.5 to 5.5 | Operating Voltage (vcc) | 3.0 to 3.6 or 4.5 to 5.5 |
| Fpu | Yes | Mpu / Mmu | Yes / No |
| Timers | 6 | Output Compare Channels | 22 |
| Input Capture Channels | 12 | Pwm Channels | 19 |
| 32khz Rtc | Yes | Calibrated Rc Oscillator | Yes |
AT32UC3A0128 PDF datasheetAT32UC3A0128 PDF datasheet #2AT32UC3C0128C PDF datasheet #3AT32UC3C0128C PDF datasheet #4
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PrevNext
CP.W – Compare Word
Architecture revision:
Architecture revision1 and higher.
Description
Performs a compare between the two operands specified. The operation is implemented by
doing a subtraction without writeback of the difference. The operation sets the status flags
according to the result of the subtraction, but does not affect the operand registers.
Operation:
I.
II.
III.
Syntax:
I.
II.
III.
Operands:
I.
II.
III.
Status Flags:
Opcode
15
0
15
0
AVR32
158
Rd - Rs;
Rd - SE(imm6);
Rd - SE(imm21);
cp.w
Rd, Rs
cp.w
Rd, imm
cp.w
Rd, imm
{d, s} ∈ {0, 1, …, 15}
d ∈ {0, 1, …, 15}
imm ∈ {-32, -31, ..., 31}
d ∈ {0, 1, …, 15}
imm ∈ {-1048576, -104875, ..., 1048575}
Format I: OP1 = Rd, OP2 = Rs
Format II: OP1 = Rd, OP2 = SE(imm6)
Format III:OP1 = Rd, OP2 = SE(imm21)
Q:
Not affected
V ← (OP1[31] ∧ ¬OP2[31] ∧ ¬RES[31]) ∨ (¬OP1[31] ∧ OP2[31] ∧ RES[31])
V:
N ← RES[31]
N:
Z ← (RES[31:0] == 0)
Z:
C ← ¬OP1[31] ∧ OP2[31] ∨ OP2[31] ∧ RES[31] ∨ ¬OP1[31] ∧ RES[31]
C:
Format I:
13
12
9
0
0
Rs
Format II:
13
12
10
9
1
0
1
1
0
8
4
3
0
0
0
1
1
4
3
imm6
0
Rd
0
Rd
32000D–04/2011
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