AT89C5115 Atmel Corporation, AT89C5115 Datasheet - Page 20

• Manufacturer Part Number: AT89C5115
• Manufacturer: Atmel Corporation

Specifications of AT89C5115

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 20
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 0.5
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Reset Recommendation
to Prevent Flash
Corruption
Idle Mode
Entering Idle Mode
Exiting Idle Mode
Power-down Mode
Entering Power-down Mode
20
AT89C5115
When a Flash program memory is embedded on-chip, it is strongly recommended to
use an external reset chip (brown out device) to apply a reset (Figure 7). It prevents sys-
tem malfunction during periods of insufficient power-supply voltage (power-supply
failure, power supply switched off, etc.).
Idle mode is a power reduction mode that reduces the power consumption. In this mode,
program execution halts. Idle mode freezes the clock to the CPU at known states while
the peripherals continue to be clocked. The CPU status before entering Idle mode is
preserved, i.e., the program counter and program status word register retain their data
for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The
status of the Port pins during Idle mode is detailed in Table 12.
To enter Idle mode, set the IDL bit in PCON register (See Table 15). The T89C5115
enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that
sets IDL bit is the last instruction executed.
Note:
There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
2. Generate a reset.
Notes:
The Power-down mode places the T89C5115 in a very low power state. Power-down
mode stops the oscillator, freezes all clock at known states. The CPU status prior to
entering Power-down mode is preserved, i.e., the program counter, program status
word register retain their data for the duration of Power-down mode. In addition, the
SFRs and RAM contents are preserved. The status of the Port pins during Power-down
mode is detailed in Table 14.
To enter Power-down mode, set PD bit in PCON register. The T89C5115 enters the
Power-down mode upon execution of the instruction that sets PD bit. The instruction
that sets PD bit is the last instruction executed.
Hardware clears IDL bit in PCON register which restores the clock to the CPU. Exe-
cution resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes with the instruction immediately follow-
ing the instruction that activated Idle mode. The general purpose flags (GF1 and
GF0 in PCON register) may be used to indicate whether an interrupt occurred dur-
ing normal operation or during Idle mode. When Idle mode is exited by an interrupt,
the interrupt service routine may examine GF1 and GF0.
A logic high on the RST pin clears IDL bit in PCON register directly and asynchro-
nously. This restores the clock to the CPU. Program execution momentarily
resumes with the instruction immediately following the instruction that activated the
Idle mode and may continue for a number of clock cycles before the internal reset
algorithm takes control. Reset initializes the T89C5115 and vectors the CPU to
address C:0000h.
If IDL bit and PD bit are set simultaneously, the T89C5115 enters Power-down mode.
Then it does not go in Idle mode when exiting Power-down mode.
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle.
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated Idle
mode should not write to a Port pin or to the external RAM.
4128G–8051–02/08