AT89C5115 Atmel Corporation, AT89C5115 Datasheet - Page 21

• Manufacturer Part Number: AT89C5115
• Manufacturer: Atmel Corporation

Specifications of AT89C5115

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 20
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 0.5
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Exiting Power-down Mode
Figure 8. Power-down Exit Waveform Using INT1:0#
4128G–8051–02/08
INT1:0#
OSC
Active phase
Note:
There are two ways to exit the Power-down mode:
1. Generate an enabled external interrupt.
Notes:
2. Generate a reset.
Notes:
–
–
Power-down phase
If
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The T89C5115 provides capability to exit from Power-down using INT0#,
INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTx# input,
execution resumes when the input is released (See Figure 8). Execution
resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes with the instruction immediately
following the instruction that activated Power-down mode.
1. The external interrupt used to exit Power-down mode must be configured as level
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the T89C5115 and vectors the
CPU to address 0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
DD
V
sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,
the duration of the interrupt must be long enough to allow the oscillator to stabilize.
The execution will only resume when the interrupt is deasserted.
RAM content.
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
RAM content.
DD
is restored to the normal operating level.
was reduced during the Power-down mode, do not exit Power-down mode until
Oscillator restart phase
Active phase
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