AT89C5115 Atmel Corporation, AT89C5115 Datasheet - Page 39

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AT89C5115

Manufacturer Part Number
AT89C5115
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C5115

Flash (kbytes)
16 Kbytes
Max. Operating Frequency
40 MHz
Cpu
8051-12C
Max I/o Pins
20
Uart
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
0.5
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART
Watchdog
Yes

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Flash Protection from Parallel
Programming
Preventing Flash Corruption
4128G–8051–02/08
Figure 17. Reading Procedure
Note:
The three lock bits in Hardware Security Byte (See ’In-System Programming’ section)
are programmed according to Table 23 provide different level of protection for the on-
chip code and data located in FM0 and FM1.
The only way to write this bits are the parallel mode. They are set by default to level 3.
Table 23. Program Lock bit
Note:
WARNING: Security level 2, 3 and 4 should only be programmed after Flash and Core
verification.
See Section “Power Management”.
Security
Level
1
2
3
4
Program Lock bits
aa = 10 for the Hardware Security Byte.
1. Program Lock bits
U: unprogrammed
P: programmed
LB0
U
P
U
U
LB1
U
U
P
U
LB2
U
U
U
P
Protection Description
No program lock features enabled.
Parallel programming of the Flash is disabled.
Same as 2, also verify through parallel programming interface is
disabled. This is the factory defaul programming.
Same as 3
Exec: MOVC A, @A+DPTR
Flash Spaces Reading
Flash Spaces Mapping
FCON = 00000aa0b
DPTR = Address
FCON = 00h
Clear Mode
Data Read
ACC= 0
39

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