AT89C5130A-M Atmel Corporation, AT89C5130A-M Datasheet - Page 118

• Manufacturer Part Number: AT89C5130A-M
• Manufacturer: Atmel Corporation

Specifications of AT89C5130A-M

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

20.3
118
Registers
AT89C5130A/31A-M
Table 20-10. SSCON Register
SSCON - Synchronous Serial Control Register (93h)
Table 20-11. SSDAT (095h) - Synchronous Serial Data Register (read/write)
Bit Number
Bit Number
CR2
SD7
7
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
Mnemonic
Mnemonic
SSIE
SSIE
CR2
CR1
CR0
SD6
SD7
SD6
SD5
SD4
SD3
SD2
STA
ST0
Bit
AA
Bit
SI
6
6
Description
Control Rate bit 2
See .
Synchronous Serial Interface Enable bit
Clear to disable SSLC.
Set to enable SSLC.
Start flag
Set to send a START condition on the bus.
Stop flag
Set to send a STOP condition on the bus.
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level on
SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on SDA).
This bit has no effect when in master transmitter mode.
Control Rate bit 1
See Table 20-4
Control Rate bit 0
See Table 20-4
Description
Address bit 7 or Data bit 7.
Address bit 6 or Data bit 6.
Address bit 5 or Data bit 5.
Address bit 4 or Data bit 4.
Address bit 3 or Data bit 3.
Address bit 2 or Data bit 2.
STA
SD5
5
5
STO
SD4
4
4
SD3
SI
3
3
SD2
AA
2
2
CR1
SD1
1
1
4337K–USB–04/08
CR0
SD0
0
0