AT89C5130A-M Atmel Corporation, AT89C5130A-M Datasheet - Page 130

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AT89C5130A-M

Manufacturer Part Number
AT89C5130A-M
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C5130A-M

Flash (kbytes)
16 Kbytes
Max. Operating Frequency
48 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
1024
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART/USB
Watchdog
Yes
21.5
21.5.1
21.5.2
21.5.3
130
Control Transactions
AT89C5130A/31A-M
Setup Stage
Data Stage: Control Endpoint Direction
Status Stage
The firmware will never write more bytes than supported by the endpoint FIFO.
The DIR bit in the UEPSTAX register will be at 0.
Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP
bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate
that an Out packet with a Setup PID has been received on the Control endpoint. When the
RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an inter-
rupt is triggered if enabled.
The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing
the RXSETUP bit to free the endpoint FIFO for the next transaction.
The data stage management is similar to Bulk management.
A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All
other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to
specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX regis-
ter.
The firmware has to use the DIR bit before data IN in order to meet the data-toggle
requirements:
To send a STALL handshake, see
The DIR bit in the UEPSTAX register will be reset at 0 for IN and OUT status stage.
The status stage management is similar to Bulk management.
• If the data stage consists of INs,
• If the data stage consists of OUTs,
• For a Control Write transaction or a No-Data Control transaction, the status stage consists of
• For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see
the firmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and
sending the data by setting to 1 the TXRDY bit in the UEPSTAX register. The IN transaction
is complete when the TXCMPL has been set by the hardware. The firmware will clear the
TXCMPL bit before any other transaction.
the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware when a new
valid packet has been received on the endpoint. The firmware must read the data stored into
the FIFO and then clear the RXOUTB0 bit to reset the FIFO and to allow the next transaction.
a IN Zero Length Packet (see
128). To send a STALL handshake, see
“Bulk/Interrupt OUT Transactions in Standard Mode” on page
“Bulk/Interrupt IN Transactions in Standard Mode” on page
“STALL Handshake” on page
“STALL Handshake” on page
133.
126).
133.
4337K–USB–04/08

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