AT89C5130A-M Atmel Corporation, AT89C5130A-M Datasheet - Page 133

• Manufacturer Part Number: AT89C5130A-M
• Manufacturer: Atmel Corporation

Specifications of AT89C5130A-M

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

21.7.2
21.7.3
21.7.4
21.7.5
21.8
21.8.1
4337K–USB–04/08
Suspend/Resume Management
STALL Handshake
Start of Frame Detection
Frame Number
Data Toggle Bit
Suspend
This function is only available for Control, Bulk, and Interrupt endpoints.
The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake
at the next request of the Host on the endpoint selected with the UEPNUM register. The
RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first reset to 0. The bit
STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an inter-
rupt if enabled.
The firmware will clear the STALLRQ and STLCRC bits after each STALL sent.
The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on
a CONTROL type endpoint.
Important note: when a Clear Halt Feature occurs for an endpoint, the firmware will reset this
endpoint using the UEPRST register in order to reset the data toggle management.
The SOFINT bit in the USBINT register is set when the USB controller detects a Start of Frame
PID. This triggers an interrupt if enabled. The firmware will clear the SOFINT bit to allow the next
Start of Frame detection.
When receiving a Start of Frame, the frame number is automatically stored in the UFNUML and
UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start of
Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The UFNUML and UFNUMH
registers are automatically updated when receiving a new Start of Frame.
The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted by the
USB controller and cleared by hardware when a DATA1 packet is received and accepted by the
USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST
register.
For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling is then
used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Sta-
tus stage completes the data transfer with a DATA1 (for a control read transfer).
For Isochronous endpoints, the device firmware will ignore the data-toggle.
The Suspend state can be detected by the USB controller if all the clocks are enabled and if the
USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for
more than 3 ms. This triggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop
the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active.
The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new
suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSP-
CLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-
up event is detected.
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