AT89C5130A-M Atmel Corporation, AT89C5130A-M Datasheet - Page 98

• Manufacturer Part Number: AT89C5130A-M
• Manufacturer: Atmel Corporation

Specifications of AT89C5130A-M

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

19.3.3
19.3.3.1
19.3.3.2
19.3.3.3
19.3.4
98
AT89C5130A/31A-M
Error Conditions
Interrupts
Mode Fault (MODF)
Write Collision (WCOL)
Overrun Condition
The following flags in the SPSTA signal SPI error conditions:
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is
inconsistent with the actual mode of the device. MODF is set to warn that there may have a
multi-master conflict for system control. In this case, the SPI system is affected in the following
ways:
When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the
SS signal becomes “0”.
However, as stated before, for a system with one Master, if the SS pin of the Master device is
pulled low, there is no way that another Master attempt to drive the network. In this case, to pre-
vent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and
therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed
by a write to the SPCON register. SPEN Control bit may be restored to its original set state after
the MODF bit has been cleared.
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done
during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an
access to SPDAT.
An overrun condition occurs when the Master device tries to send several data bytes and the
Slave devise has not cleared the SPIF bit issuing from the previous data byte transmitted. In this
case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the
SPDAT returns this byte. All others bytes are lost.
This condition is not detected by the SPI peripheral.
Two SPI status flags can generate a CPU interrupt requests:
Table 19-2.
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been
completed. SPIF bit generates transmitter CPU interrupt requests.
Flag
SPIF (SP Data Transfer)
MODF (Mode Fault)
• An SPI receiver/error CPU interrupt request is generated,
• The SPEN bit in SPCON is cleared. This disable the SPI,
• The MSTR bit in SPCON is cleared
SPI Interrupts
Request
SPI Transmitter Interrupt request
SPI Receiver/Error Interrupt Request (if SSDIS = “0”)
4337K–USB–04/08