AT89C5131A-L Atmel Corporation, AT89C5131A-L Datasheet - Page 4

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AT89C5131A-L

Manufacturer Part Number
AT89C5131A-L
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C5131A-L

Flash (kbytes)
32 Kbytes
Max. Operating Frequency
48 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
1024
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 3.6
Timers
4
Isp
UART/USB
Watchdog
Yes
Mapping and Default
Value of Hardware
Security Byte
Security
4
AT89C5131A USB Bootloader
The 4 MSB of the Hardware Byte can be read/written by software (this area is called Fuse bits).
The 4 LSB can only be read by software and written by hardware in parallel mode (with parallel
programmer devices).
Note:
The bootloader has Software Security Byte (SSB) to protect itself from user access or ISP
access.
The Software Security Byte (SSB) protects from ISP accesses. The command "Program Soft-
ware Security Bit" can only write a higher priority level. There are three levels of security:
Only a full chip erase command can reset the software security bits.
Level 0: NO_SECURITY (FFh)
This is the default level.
From level 0, one can write level 1 or level 2.
Level 1: WRITE_SECURITY (FEh)
In this level it is impossible to write in the Flash memory.
The Bootloader returns an err_WRITE status.
From level 1, one can write only level 2.
Level 2: RD_WR_SECURITY (FCh)
Level 2 forbids all read and write accesses to/from the Flash memory.
The Bootloader returns an err_WRITE or an err_VENDOR status.
Flash/EEPROM
Fuse bit
BSB & SBV & EB Any access allowed
SSB
Manufacturer info Read only access allowed
Bootloader info
Erase block
Full chip erase
Blank Check
Bit Position
U: Unprogrammed = 1
P: Program = 0
7
6
5
4
3
2
1
0
Mnemonic
OSCON1
OSCON0
reserved
BLJB
Level 0
Any access allowed
Any access allowed
Any access allowed
Read only access allowed
Allowed
Allowed
Allowed
X2B
LB2
LB1
LB0
Default Value
U
P
U
U
U
P
U
U
Description
To start in x1 mode
To map the boot area in code area between F800h-FFFFh
Oscillator control (bit 1)
Oscillator control (bit 0)
To lock the chip (see datasheet)
Level 1
Read only access allowed
Read only access allowed
Any access allowed
Write level2 allowed
Read only access allowed
Read only access allowed
Not allowed
Allowed
Allowed
Level 2
All access not allowed
All access not allowed
Any access allowed
Read only access allowed
Read only access allowed
Read only access allowed
Not allowed
Allowed
Allowed
4287E–USB–04/08

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