AT89C5131A-M

Manufacturer Part NumberAT89C5131A-M
ManufacturerAtmel Corporation
AT89C5131A-M datasheets
 


Specifications of AT89C5131A-M

Flash (kbytes)32 KbytesMax. Operating Frequency48 MHz
Cpu8051-12CMax I/o Pins34
Usb Transceiver1Usb SpeedFull Speed
Usb InterfaceDeviceSpi1
Twi (i2c)1Uart1
Sram (kbytes)1.25Eeprom (bytes)1024
Self Program MemoryAPIOperating Voltage (vcc)2.7 to 5.5
Timers4IspUART/USB
WatchdogYes  
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Features
80C52X2 Core (6 Clocks per Instruction)
– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode
– Dual Data Pointer
– Full-duplex Enhanced UART (EUART)
– Three 16-bit Timer/Counters: T0, T1 and T2
– 256 Bytes of Scratchpad RAM
16/32-Kbyte On-chip Flash EEPROM In-System Programming through USB
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
3-KbyteFlash EEPROM for Bootloader
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
1-Kbyte EEPROM Data (
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
On-chip Expanded RAM (ERAM): 1024 Bytes
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers: 32-byte FIFO
– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
• Endpoint 1, 2, 3: 32-byte FIFO
• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)
• Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode)
– Suspend/Resume Interrupts
– 48 MHz PLL for Full-speed Bus Operation
– Bus Disconnection on Microcontroller Request
5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed
Output, Compare/Capture, PWM and Watchdog Timer Capabilities
Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 100 ms
to 3s at 8 MHz
Keyboard Interrupt Interface on Port P1 (8 Bits)
TWI (Two Wire Interface) 400Kbit/s
SPI Interface (Master/Slave Mode)
34 I/O Pins
4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical
4-level Priority Interrupt System (11 sources)
Idle and Power-down Modes
0 to 24 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis
Industrial Temperature Range
Extended Range Power Supply: 2.7V to 5.5V (3.3V to 5.5V required for USB)
Packages: PLCC52, VQFP64, QFN32
8-bit Flash
Microcontroller
with Full Speed
USB Device
AT89C5130A-M
AT89C5131A-M

AT89C5131A-M Summary of contents

  • Page 1

    ... Idle and Power-down Modes • MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis • Industrial Temperature Range • Extended Range Power Supply: 2.7V to 5.5V (3.3V to 5.5V required for USB) • Packages: PLCC52, VQFP64, QFN32 8-bit Flash Microcontroller with Full Speed USB Device AT89C5130A-M AT89C5131A-M ...

  • Page 2

    Description AT89C5130A/31A high-performance Flash version of the 80C51 single-chip 8-bit micro- controllers with full speed USB functions. AT89C5130A/31A-M features a full-speed USB module compatible with the USB specifications Version 1.1 and 2.0. This module integrates the USB ...

  • Page 3

    Block Diagram XTAL1 XTAL2 ALE PSEN CPU EA (2) RD (2) WR Notes: 1. Alternate function of Port 1 2. Alternate function of Port 3 3. Alternate function of Port 4 4337K–USB–04/08 (2) (2) EEPROM EUART 16/32Kx8Flash 4Kx8 RAM ...

  • Page 4

    Pinout Description 3.1 Pinout Figure 3-1. AT89C5130A/31A-M 4 AT89C5130A/31A-M 52-pin PLCC Pinout P4.1/SDA 8 9 P2.3/A11 P2.4/A12 10 P2.5/A13 11 12 XTAL2 13 XTAL1 PLCC52 14 P2.6/A14 P2.7/A15 15 VDD 16 AVDD ...

  • Page 5

    Figure 3-2. 4337K–USB–04/08 AT89C5130A/31A-M 64-pin VQFP Pinout P2.3/A11 3 P2.4/A12 4 P2.5/A13 5 XTAL2 6 XTAL1 7 P2.6/A14 8 P2.7/A15 VQFP64 9 VDD 10 AVDD ...

  • Page 6

    Figure 3-3. 3.2 Signals All the AT89C5130A/31A-M signals are detailed by functionality on Table 3-1 through Table 3- 12. Table 3-1. Table 3-2. AT89C5130A/31A-M 6 AT89C5130A/31A-M 32-pin QFN Pinout P4.1/SDA 1 XTAL2 ...

  • Page 7

    Table 3-3. Table 3-4. 4337K–USB–04/08 Signal Name Type Description Capture External Input CEX[4:0] I/O Compare External Output Serial I/O Signal Description Signal Name Type Description RxD I Serial Input Port TxD O Serial Output Port Timer 0, Timer 1 and ...

  • Page 8

    Table 3-5. Table 3-6. Table 3-7. AT89C5130A/31A-M 8 LED Signal Description Signal Name Type Description Direct Drive LED Output These pins can be directly connected to the Cathode of standard LEDs LED[3:0] O without external current limiting resistors. The typical ...

  • Page 9

    Table 3-8. Table 3-9. 4337K–USB–04/08 Ports Signal Description Signal Name Type Description Port 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used P0[7:0] I/O as high ...

  • Page 10

    Table 3-10. Table 3-11. Table 3-12. AT89C5130A/31A-M 10 USB Signal Description Signal Name Type Description USB Data + signal D+ I/O Set to high level under reset. USB Data - signal D- I/O Set to low level under reset. USB ...

  • Page 11

    Table 3-12. 4337K–USB–04/08 Power Signal Description (Continued) Signal Name Type Description Analog Supply Voltage AVDD PWR AVDD is used to supply the on-chip PLL and the USB PAD. Digital Ground VSS GND VSS is used to supply the buffer ring ...

  • Page 12

    Typical Application 4.1 Recommended External components All the external components described in the figure below must be implemented as close as pos- sible from the microcontroller package. The following figure represents the typical wiring schematic. Figure 4-1. VDD USB ...

  • Page 13

    PCB Recommandations Figure 4-2. Figure 4-3. 4337K–USB–04/08 USB Pads Components must be close to the microcontroller VRef possible, isolate D+ and D- signals from other signals with ground wires USB PLL Components must be close to ...

  • Page 14

    Clock Controller 5.1 Introduction The AT89C5130A/31A-M clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller. The AT89C5130A/31A-M X1 ...

  • Page 15

    In order to optimize the power consumption, the oscillator inverter is inactive when the PLL out- put is not selected for the USB device. Figure 5-2. 5.3 PLL 5.3.1 PLL Description The AT89C5130A/31A-M PLL is used to generate internal high ...

  • Page 16

    Figure 5-4. The typical values are 100 Ω nf 2.2 nF. 5.3.2 PLL Programming The PLL is programmed using the flow shown in Figure 5-5. As soon as clock generation is enabled user ...

  • Page 17

    Registers Table 5-2. 4337K–USB–04/08 Oscillator Frequency 32 MHz 40 MHz CKCON0 (S:8Fh) Clock Control Register TWIX2 WDX2 PCAX2 Bit Bit Number Mnemonic Description TWI Clock This control bit is validated when the CPU clock X2 ...

  • Page 18

    Reset Value = 0000 0000b Table 5-3. Reset Value = 0000 0000b Table 5-4. Reset Value = 0000 0000b Table 5-5. AT89C5130A/31A-M 18 CKCON1 (S:AFh) Clock Control Register Bit Bit Number Mnemonic Description ...

  • Page 19

    Reset Value = 0000 0000 4337K–USB–04/08 Bit Bit Number Mnemonic Description 7-4 R3:0 PLL R Divider Bits 3-0 N3:0 PLL N Divider Bits AT89C5130A/31A-M 19 ...

  • Page 20

    SFR Mapping The Special Function Registers (SFRs) of the AT89C5130A/31A-M fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4 • Timer registers: T2CON, T2MOD, ...

  • Page 21

    The table below shows all SFRs with their address and their reset value. Table 6-1. SFR Descriptions Bit Addressable 0/8 1/9 CH UEPINT F8h 0000 0000 0000 0000 LEDCON B F0h 0000 0000 0000 0000 CL E8h 0000 0000 ACC ...

  • Page 22

    The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories: Table 6-2. Table 6-3. Table 6-4. Timer SFR’s Mnemonic Add Name TH0 8Ch Timer/Counter 0 High byte TL0 8Ah Timer/Counter 0 Low byte TH1 8Dh Timer/Counter 1 ...

  • Page 23

    Table 6-4. Timer SFR’s (Continued) Mnemonic Add Name Timer/Counter 2 RCAP2H CBh Reload/Capture High byte Timer/Counter 2 RCAP2L CAh Reload/Capture Low byte WDTRST A6h WatchDog Timer Reset WDTPRG A7h WatchDog Timer Program Table 6-5. Serial I/O Port SFR’s Mnemonic Add ...

  • Page 24

    Table 6-7. PCA SFR’s Mnemo- nic Add Name CCAP0 PCA Compare Capture Module CCAP1 PCA Compare Capture Module 1 FAh H H FBh CCAP2 PCA Compare Capture Module 2 FCh H H FDh CCAP3 PCA Compare Capture ...

  • Page 25

    Table 6-10. Keyboard SFRs Mnemonic Add Name Keyboard Level KBLS 9Ch Selector Register Table 6-11. TWI SFRs Mnemonic Add Name Synchronous Serial SSCON 93h Control Synchronous Serial SSCS 94h Control-Status Synchronous Serial SSDAT 95h Data Synchronous Serial SSADR 96h Address ...

  • Page 26

    Table 6-13. USB SFR’s Mnemonic Add Name USB Byte Counter Low UBYCTLX E2h (EP X) USB Byte Counter High UBYCTHX E3h (EP X) USB Frame Number UFNUML BAh Low USB Frame Number UFNUMH BBh High Table 6-14. Other SFR’s Mnemonic ...

  • Page 27

    Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data ...

  • Page 28

    ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 ; 0000 909000MOV DPTR,#SOURCE ; address ...

  • Page 29

    ... I/O Ports 0 and 2 due to external prefetch. Fetching code constant from this location does not affect Ports 0 and 2. AT89C5130A/31A-M voltage. Thus, the Flash Mem- DD FFFFh 32 Kbytes External Code 8000h 7FFFh 32 Kbytes Flash 0000h AT89C5131A 29 ...

  • Page 30

    Figure 8-2. Table 8-1. 8.1.2 External Bus Cycles This section describes the bus cycles the AT89C5130A/31A-M executes to fetch code (see Figure 8-3) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to ...

  • Page 31

    ... Hardware Security (1 Byte) Extra Row (128 Bytes) Column Latches (128 Bytes) 3FFFh for AT89C5130A for 16 KB 7FFFh for AT89C5131A for 32 KB 8.2.1 FM0 Memory Architecture The Flash memory is made blocks (see Figure 8-4): 1. The memory array (user space) 32 Kbytes 2. The Extra Row 3 ...

  • Page 32

    Column Latches The column latches, also part of FM0, have a size of full page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XRow and Hardware security byte). 8.3 Overview ...

  • Page 33

    Table 8-3. The Flash memory enters a busy state as soon as programming is launched. In this state, the memory is not available for fetching code. Thus to avoid any erratic execution during program- ming, the CPU enters Idle mode. ...

  • Page 34

    Figure 8-5. 8.3.6 Programming the Flash Spaces 8.3.6.1 User The following procedure is used to program the User space and is summarized in Figure 8-6: • Load data in the column latches from address 0000h to 7FFFh • Disable the ...

  • Page 35

    Figure 8-6. 8.3.6.3 Hardware Security The following procedure is used to program the Hardware Security space and is summarized in Figure 8-7: • Set FPS and map Hardware byte (FCON = 0x0C) • Disable the interrupts. • Load DPTR at ...

  • Page 36

    Figure 8-7. 8.3.7 Reading the Flash Spaces 8.3.7.1 User The following procedure is used to read the User space and is summarized in Figure 8-8: • Map the User space by writing 00h in FCON register. • Read one byte ...

  • Page 37

    Hardware Security The following procedure is used to read the Hardware Security space and is summarized in Figure 8-8: • Map the Hardware Security space by writing 04h in FCON register. • Read the byte in Accumulator by executing ...

  • Page 38

    Flash EEPROM Memory 9.1 General Description The Flash memory increases EPROM functionality with in-circuit electrical erasure and program- ming. It contains 16/32 Kbytes of program memory organized in 128/256 pages of 128 bytes, respectively. This memory is both parallel ...

  • Page 39

    Flash Registers and Memory Map The AT89C5130A/31A-M Flash memory uses several registers: • Hardware register can be accessed with a parallel programmer.Some bits of the hardware register can be changed, also, by API (i.e. X2 and BLJB bits of ...

  • Page 40

    Table 9-2. Notes: These security bits protect the code access through the parallel programming interface. They are set by default to level 4. The code access through the ISP is still possible and is controlled by the “software security bits” ...

  • Page 41

    Table 9-3. After programming the part by ISP, the BSB must be cleared (00h) in order to allow the applica- tion to boot at 0000h. The content of the Software Security Byte (SSB) is described in To assure code protection ...

  • Page 42

    ... Flash Memory Status AT89C5130A/31A-M parts are delivered with the ISP boot in the Flash memory. After ISP or par- allel programming, the possible contents of the Flash memory are summarized in Figure 9-1. Flash Memory Possible Contents 3FFFh AT89C5130A-M 7FFFh AT89C5131A-M Virgin Application 0000h Default After ISP 9 ...

  • Page 43

    EEPROM Data Memory 10.1 Description The 1-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 03FFh of the ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM ...

  • Page 44

    Registers Table 10-1. Reset Value = XXXX XX00b Not bit addressable AT89C5130A/31A-M 44 EECON (S:0D2h) EECON Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch command bits 7-4 EEPL3-0 Write 5Xh followed by AXh ...

  • Page 45

    In-System Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technol- ogy the AT89C5130A/31A-M allows the system engineer the development of applications with a very high level of flexibility. This flexibility ...

  • Page 46

    Figure 11-1. Flash Memory Mapping 3FFFh Custom Bootloader [SBV]00h 16K Bytes Flash Memory FM0 0000h C5130A 11.2 Boot Process 11.2.1 Software Boot Process Example Many algorithms can be used for the software boot process. Below are descriptions of the differ- ...

  • Page 47

    Figure 11-2. Hardware Boot Process Algorithm ENBOOT = 0000h Application in FM0 11.3 Application-Programming-Interface Several Application Program Interface (API) calls are available for use by an application pro- gram to permit selective erasing and programming of Flash ...

  • Page 48

    Hardware Conditions It is possible to force the controller to execute the bootloader after a Reset with hardware condi- tions. Depending on the product type (low pin count or high pin count package), there are two methods to apply ...

  • Page 49

    Figure 11-4. Hardware conditions typical sequence during power-on. 11.5.2 Low Pin Count Hardware Conditions (QFN32) Low pin count products do not have PSEN signal, thus for these products, the bootloader is always executed after reset thanks to the BLJB bit. ...

  • Page 50

    On-chip Expanded RAM (ERAM) The AT89C5130A/31A-M provides additional Bytes of random access memory (RAM) space for increased data parameters handling and high level language usage. AT89C5130A/31A-M devices have expanded RAM in external data space; maximum size and location are ...

  • Page 51

    Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: ...

  • Page 52

    Reset Value = 0X0X 1100b Not bit addressable AT89C5130A/31A-M 52 Bit Bit Number Mnemonic Description Pulse length Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock 5 M0 periods (default). Set to stretch MOVX ...

  • Page 53

    Timer 2 The Timer 2 in the AT89C5130A/31A-M is the standard C52 Timer 16-bit timer/counter: the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2 controlled by T2CON (Table 13-1) ...

  • Page 54

    Figure 13-1. Auto-reload Mode Up/Down Counter (DCEN = 1) F CLK PERIPH 13.2 Programmable Clock Output In the Clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 13-2). The input clock increments TL2 at frequency F ...

  • Page 55

    It is possible to use Timer baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both func- tions use the values in the RCAP2H and ...

  • Page 56

    Table 13-1. 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT89C5130A/31A-M 56 T2CON Register T2CON - Timer 2 Control Register (C8h EXF2 RCLK TCLK Bit Mnemonic ...

  • Page 57

    Table 13- Bit Number Reset Value = XXXX XX00b Not bit addressable 4337K–USB–04/08 T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit ...

  • Page 58

    Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time ...

  • Page 59

    Figure 14-1. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH T0 OVF P1.2 Idle Table 14-1. 7 CIDL Bit Number 4337K–USB–04/08 CH CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 ...

  • Page 60

    Reset Value = 00XX X000b Not bit addressable The CMOD register includes three additional bits associated with the PCA (See Figure 14-1 and Table 14-1). • The CIDL bit allows the PCA to stop during idle mode. • The WDTE ...

  • Page 61

    Bit Number 1 0 Reset Value = 000X 0000b Not bit addressable The watchdog timer function is implemented in module 4 (See Figure 14-4). The PCA interrupt system is shown in Figure 14-2. Figure 14-2. PCA Interrupt System PCA Timer/Counter ...

  • Page 62

    The ECCF bit (CCAPMn.0 where depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. ...

  • Page 63

    Bit Number 1 0 Reset Value = X000 0000b Not bit addressable Table 14-4. ECOMn There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL ...

  • Page 64

    Reset Value = XXXX XXXXb Not bit addressable Table 14-6. CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) ...

  • Page 65

    PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on ...

  • Page 66

    Figure 14-4. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 Note: Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match ...

  • Page 67

    Figure 14-5. PCA High-speed Output Mode Write to Reset CCAPnL Write to CCAPnH 0 1 Enable Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match could happen. Once ECOM ...

  • Page 68

    Figure 14-6. PCA PWM Mode 14.5 PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, ...

  • Page 69

    Serial I/O Port The serial I/O port in the AT89C5130A/31A-M is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter (UART) ...

  • Page 70

    Figure 15-3. UART Timings in Modes 2 and 3 15.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition ...

  • Page 71

    Slave C:SADDR1111 0011b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t care bit; for slaves B and C, bit communicate ...

  • Page 72

    SADEN - Slave Address Mask Register (B9h) 7 Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h) 7 Reset Value = 0000 0000b Not bit addressable 15.3 Baud Rate Selection for UART for Mode 1 ...

  • Page 73

    Baud Rate Selection Table for UART TCLK RCLK (T2CON) (T2CON 15.3.2 Internal Baud Rate Generator (BRG) When the internal Baud Rate ...

  • Page 74

    Bit Number Reset Value = 0000 0000b Bit addressable AT89C5130A/31A-M 74 Bit Mnemonic Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop ...

  • Page 75

    Example of computed value when SMOD1 = 1, SPD = 1 Baud Rates 115200 Example of computed value when SMOD1 = 0, SPD = 0 Baud Rates The baud rate generator can be used ...

  • Page 76

    BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) 7 – Reset Value = 0000 0000b Table 15-2. T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number ...

  • Page 77

    Table 15-3. PCON - Power Control Register (87h) 7 SMOD1 Bit Number Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on ...

  • Page 78

    Bit Number Reset Value = XXX0 0000b Not bit addressable AT89C5130A/31A-M 78 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit Reserved - ...

  • Page 79

    Interrupt System 16.1 Overview The AT89C5130A/31A-M has a total of 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the ...

  • Page 80

    Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 16-3.) and in the Interrupt Priority High register each combination. 16.2 Registers The ...

  • Page 81

    Bit Number Reset Value = 0000 0000b Bit addressable Table 16-3. IPL0 - Interrupt Priority Register (B8h 4337K–USB–04/08 Bit Mnemonic Description Enable All interrupt bit EA Cleared to disable all ...

  • Page 82

    Bit Number Reset Value = X000 0000b Bit addressable Table 16-4. IPH0 - Interrupt Priority High Register (B7h AT89C5130A/31A-M 82 Bit Mnemonic Description Reserved - The value read from this ...

  • Page 83

    Bit Number Reset Value = X000 0000b Not bit addressable Table 16-5. 4337K–USB–04/08 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. PCA ...

  • Page 84

    IEN1 - Interrupt Enable Register (B1h Bit Number AT89C5130A/31A EUSB - - Bit Mnemonic Description - Reserved USB Interrupt Enable bit EUSB Cleared to disable USB ...

  • Page 85

    Reset Value = X0XX X000b Not bit addressable Table 16-6. IPL1 - Interrupt Priority Register (B2h Bit Number Reset Value = X0XX X000b Not bit addressable 4337K–USB–04/08 IPL1 Register 6 ...

  • Page 86

    Table 16-7. IPH1 - Interrupt Priority High Register (B3h Bit Number Reset Value = X0XX X000b Not bit addressable AT89C5130A/31A-M 86 IPH1 Register PUSBH - - Bit ...

  • Page 87

    Interrupt Sources and Vector Addresses Table 16-8. Number 4337K–USB–04/08 Vector Table Polling Interrupt Priority Source 0 0 Reset 1 1 INT0 2 2 Timer INT1 4 4 Timer UART 6 7 Timer 2 ...

  • Page 88

    Keyboard Interface 17.1 Introduction The AT89C5130A/31A-M implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are ...

  • Page 89

    Power Reduction Mode P1 inputs allow exit from idle and power down modes as detailed in section “Power-down Mode”. 17.3 Registers Table 17-1. KBF - Keyboard Flag Register (9Eh) 7 KBF7 Bit Number ...

  • Page 90

    Table 17-2. KBE - Keyboard Input Enable Register (9Dh) 7 KBE7 Bit Number Reset Value = 0000 0000b AT89C5130A/31A-M 90 KBE Register KBE6 KBE5 KBE4 Bit Mnemonic Description Keyboard ...

  • Page 91

    Table 17-3. KBLS-Keyboard Level Selector Register (9Ch) 7 KBLS7 Bit Number Reset Value = 0000 0000b 4337K–USB–04/08 KBLS Register KBLS6 KBLS5 KBLS4 Bit Mnemonic Description Keyboard line 7 Level ...

  • Page 92

    Programmable LED AT89C5130A/31A-M have programmable LED current sources, configured by the regis- ter LEDCON. Table 18-1. LEDCON (S:F1h) LED Control Register 7 Bit Number 7:6 5:4 3:2 1:0 Reset Value = 00h AT89C5130A/31A-M 92 LEDCON Register ...

  • Page 93

    Serial Peripheral Interface (SPI) The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communica- tion between the MCU and peripheral devices, including other MCUs. 19.1 Features Features of the SPI module include the following: • Full-duplex, three-wire synchronous ...

  • Page 94

    SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines driven by the Master for eight clock cycles which allows to exchange ...

  • Page 95

    SPR2 1 19.3 Functional Description Figure 19-2 Figure 19-2. SPI Module Block Diagram 19.3.1 Operating Modes The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Slave mode. The configuration and initialization of the ...

  • Page 96

    When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex trans- mission with both data out and data ...

  • Page 97

    Figure 19-5). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device. Figure 19-4. Data Transmission Format (CPHA = 0) SCK cycle number SPEN (internal) ...

  • Page 98

    Error Conditions The following flags in the SPSTA signal SPI error conditions: 19.3.3.1 Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode ...

  • Page 99

    Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. Figure 19-7 gives a logical view of ...

  • Page 100

    Bit Number Reset Value = 0001 0100b Not bit addressable 19.3.5.2 Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write collision • Inconsistent ...

  • Page 101

    Bit Number Reset Value = 00X0 XXXXb Not Bit addressable 19.3.5.3 Serial Peripheral Data Register (SPDAT) The Serial Peripheral Data Register ter. A write to SPDAT places data directly into the shift register. No transmit ...

  • Page 102

    Two Wire Interface ( This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial com- munication standard designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two ...

  • Page 103

    Figure 20-2. Block Diagram Input Filter SDA Output Stage Input Filter SCL Output Stage 4337K–USB–04/08 Address Register SSADR Comparator SSDAT Shift Register Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow Control Register SSCON Status ...

  • Page 104

    Description The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the Synchronous Serial Control register (SSCON; ter (SSDAT; 12) and the Synchronous Serial Address register (SSADR SSCON is used to enable the TWI ...

  • Page 105

    R : Read bit (high level at SDA Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P : STOP condition In ...

  • Page 106

    The serial interrupt flag SI must then be cleared before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, ...

  • Page 107

    Slave Transmitter Mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 20-7). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the ...

  • Page 108

    CR2 CR1 CR0 AT89C5130A/31A-M 108 Bit Frequency ( kHz MHz MHz OSCA OSCA - - 100 133.3 200 266.6 0.5 <. < ...

  • Page 109

    Figure 20-4. Format and State in the Master Transmitter Mode Successfull S transmission to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte ...

  • Page 110

    Table 20-5. Status in Master Transmitter Mode Status Status of the Two- Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT A START condition has 08h Write SLA+W been transmitted Write SLA+W A repeated START 10h condition has been ...

  • Page 111

    Figure 20-5. Format and State in the Master Receiver Mode Successfull transmission S SLA to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or ...

  • Page 112

    Table 20-6. Status in Master Receiver Mode Status Status of the Two- Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT A START condition has 08h Write SLA+R been transmitted Write SLA+R A repeated START 10h condition has been ...

  • Page 113

    Figure 20-6. Format and State in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged. Last data byte received is not acknowledged. Arbitration lost as master and addressed as slave ...

  • Page 114

    Table 20-7. Status in Slave Receiver Mode Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Own SLA+W has been 60h received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+W has been 68h received; ...

  • Page 115

    Table 20-7. Status in Slave Receiver Mode (Continued) Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Previously addressed with general call; data has been 98h received; NOT ACK has been returned A STOP condition or repeated START ...

  • Page 116

    Figure 20-7. Format and State in the Slave Transmitter Mode Reception of the S own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave ...

  • Page 117

    Table 20-8. Status in Slave Transmitter Mode (Continued) Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Data byte in SSDAT has been C0h transmitted; NOT ACK has been received Last data byte in SSDAT has C8h been ...

  • Page 118

    Registers Table 20-10. SSCON Register SSCON - Synchronous Serial Control Register (93h) 7 CR2 Bit Number Table 20-11. SSDAT (095h) - Synchronous Serial Data Register (read/write) SD7 7 Bit Number 7 ...

  • Page 119

    Bit Number 1 0 Table 20-12. SSCS (094h) Read - Synchronous Serial Control and Status Register 7 SC4 Bit Number Table 20-13. SSADR (096h) - Synchronous Serial Address Register (read/write ...

  • Page 120

    USB Controller . 21.1 Description The USB device controller provides the hardware that the AT89C5131 needs to interface a USB link to a data flow stored in a double port memory (DPRAM). The USB controller requires a 48 MHz ...

  • Page 121

    Address checking. • Clock generation (via DPLL). Figure 21-2. SIE Block Diagram End of Packet Detection Start of Packet Detection D+ D- Clk48 (48 MHz) 21.1.2 Function Interface Unit (FIU) The Function Interface Unit provides the interface between the ...

  • Page 122

    Figure 21-3. UFI Block Diagram FIU DPLL SIE Figure 21-4. Minimum Intervention from the USB Device Firmware OUT Transactions: HOST OUT DATA0 (n bytes) UFI C51 IN Transactions: IN HOST UFI NACK C51 Endpoint FIFO write 21.2 Configuration 21.2.1 General ...

  • Page 123

    Set configuration The CONFG bit in the USBCON register has to be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit has to be cleared. 21.2.2 Endpoint Configuration • Selection of an Endpoint The endpoint register ...

  • Page 124

    The Endpoint 0 is the Default Control Endpoint and will always be configured in Control type. • Endpoint direction configuration For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of the UEPCONX register with the ...

  • Page 125

    Figure 21-6. Endpoint FIFO Configuration UEPSTA0 Endpoint 0 UEPSTA6 Endpoint 6 21.3.2 Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the ...

  • Page 126

    Bulk/Interrupt OUT Transactions in Standard Mode Figure 21-7. Bulk/Interrupt OUT transactions in Standard Mode An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on ...

  • Page 127

    Bulk/Interrupt OUT Transactions in Ping-pong Mode Figure 21-8. Bulk/Interrupt OUT Transactions in Ping-pong Mode An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on ...

  • Page 128

    A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released by the firmware. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be ...

  • Page 129

    Bulk/Interrupt IN Transactions in Ping-pong Mode Figure 21-10. Bulk/Interrupt IN Transactions in Ping-pong Mode An endpoint will be first enabled and configured before being able to send Bulk or Interrupt packets. The firmware will fill the FIFO bank 0 ...

  • Page 130

    The firmware will never write more bytes than supported by the endpoint FIFO. 21.5 Control Transactions 21.5.1 Setup Stage The DIR bit in the UEPSTAX register will Receiving Setup packets is the same as receiving Bulk Out ...

  • Page 131

    Isochronous Transactions 21.6.1 Isochronous OUT Transactions in Standard Mode An endpoint will be first enabled and configured before being able to receive Isochronous packets. When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by ...

  • Page 132

    The firmware has to clear one of these two bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank. If the Host sends more bytes than supported by the endpoint ...

  • Page 133

    STALL Handshake This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake at the next request of the Host on the ...

  • Page 134

    The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Clear suspend interrupt bit in USBINT (required to allow the USB pads to enter power down mode). 2. Enable USB resume interrupt. ...

  • Page 135

    When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP, the firmware will set to 1 the RMWUPE bit in the USBCON register to enable this functionality. RMWUPE value will the other cases. If the device is in ...

  • Page 136

    Figure 21-13. Example of V Figure 21-14. Disconnect Timing D+ V (min) IHZ Disconnected 21.10 USB Interrupt System 21.10.1 Interrupt System Priorities Figure 21-15. USB Interrupt Control System D+ USB Controller D- Table 21-2. AT89C5130A/31A-M ...

  • Page 137

    USB Interrupt Control System As shown in Figure 21-16, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data (see when the Host accept a In packet. • RXOUTB0: Received Out Data Bank 0 (see hardware when ...

  • Page 138

    Figure 21-16. USB Interrupt Control Block Diagram Endpoint 0..6) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.0 AT89C5130A/31A-M 138 ...

  • Page 139

    USB Registers Table 21-3. 7 USBE Bit Number Reset Value = 00h 4337K–USB–04/08 USBCON Register USBCON (S:BCh) USB Global Control Register SUSPCLK SDRMWUP DETACH Bit Mnemonic Description USB ...

  • Page 140

    Table 21- Bit Number 7 Reset Value = 00h AT89C5130A/31A-M 140 USBINT Register USBINT (S:BDh) USB Global Interrupt Register WUPCPU EORINT Bit Mnemonic Description Reserved - The value ...

  • Page 141

    Table 21- Bit Number 7 Reset Value = 10h 4337K–USB–04/08 USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register EWUPCPU EEORINT Bit Mnemonic Description Reserved - The value ...

  • Page 142

    Table 21-6. 7 FEN Bit Number 7 6-0 Reset Value = 80h Table 21- Bit Number 7-4 3-0 Reset Value = 00h AT89C5130A/31A-M 142 USBADDR Register USBADDR (S:C6h) USB Address Register UADD6 UADD5 UADD4 Bit ...

  • Page 143

    Table 21-8. 7 EPEN Bit Number 1-0 Note: Reset Value = 80h when UEPNUM = 0 (default Control Endpoint) Reset Value = 00h otherwise for all other endpoints 4337K–USB–04/08 UEPCONX Register UEPCONX (S:D4h) USB ...

  • Page 144

    Table 21-9. 7 DIR Bit Bit Number Mnemonic Description Control Endpoint Direction This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register”). 7 DIR This bit ...

  • Page 145

    Table 21-10. UEPDATX Register 7 FDAT7 Bit Number Reset Value = XXh Table 21-11. UBYCTLX Register 7 BYCT7 Bit Number Reset Value = 00h 4337K–USB–04/08 UEPDATX (S:CFh) USB FIFO Data Endpoint ...

  • Page 146

    Table 21-12. UBYCTHX Register 7 - Bit Number 7-2 2-0 Reset Value = 00h AT89C5130A/31A-M 146 UBYCTHX (S:E3h) USB Byte Count High Register EPNUM set in UEPNUM Register UEP Bit Mnemonic ...

  • Page 147

    Table 21-13. UEPRST Register 7 - Bit Number Reset Value = 00h 4337K–USB–04/08 UEPRST (S:D5h) USB Endpoint FIFO Reset Register EP6RST EP5RST EP4RST Bit Mnemonic Description Reserved - The ...

  • Page 148

    Table 21-14. UEPINT Register 7 - Bit Number Reset Value = 00h AT89C5130A/31A-M 148 UEPINT (S:F8h read-only) USB Endpoint Interrupt Register EP6INT EP5INT EP4INT Bit Mnemonic Description Reserved - ...

  • Page 149

    Table 21-15. UEPIEN Register 7 - Bit Number Reset Value = 00h 4337K–USB–04/08 UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register EP6INTE EP5INTE EP4INTE Bit Mnemonic Description Reserved - The ...

  • Page 150

    Table 21-16. UFNUMH Register 7 - Bit Number 2-0 Reset Value = 00h Table 21-17. UFNUML Register 7 FNUM7 Bit Number Reset Value = 00h AT89C5130A/31A-M 150 UFNUMH (S:BBh, read-only) USB Frame Number High ...

  • Page 151

    Reset 22.1 Introduction The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 22-1. Reset schematic 22.2 Reset Input The Reset input can be used to force a reset pulse longer than the internal reset ...

  • Page 152

    ... Figure 22-3. Recommended Reset Output Schematic AT89C5130A/31A-M 152 VDD RST RST AT89C5131A-M 1K VSS + VSS To other on-board circuitry 4337K–USB–04/08 ...

  • Page 153

    Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an ...

  • Page 154

    Figure 23-2. Power Fail Detect Vcc Reset Vcc When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL ...

  • Page 155

    Power Management 24.1 Idle Mode An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the ...

  • Page 156

    Figure 24-1. Power-down Exit Waveform INT0 INT1 XTAL Active Phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter- rupt does no affect the SFRs. Exit from power-down by either reset or external interrupt ...

  • Page 157

    Registers Table 24-2. PCON (S:87h) Power Control Register 7 SMOD1 Bit Number Reset Value = 10h 4337K–USB–04/08 PCON Register SMOD0 - POF Bit Mnemonic Description Serial Port Mode ...

  • Page 158

    Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is ...

  • Page 159

    Table 25- Bit Number Reset value = XXXX X000 25.2 WDT During Power-down and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power- ...

  • Page 160

    Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with exter- nal program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...

  • Page 161

    Electrical Characteristics 27.1 Absolute Maximum Ratings Ambient Temperature Under Bias industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage on V from V ......................................-0. Voltage on Any Pin from ...

  • Page 162

    Notes: 1. Operating I is measured with all output pins disconnected; XTAL1 driven with 0.5V 0.5V; XTAL2 N.C RST = Port 27-1.). 2. Idle ...

  • Page 163

    Figure 27-3. I Figure 27-4. Clock Signal Waveform for I 27.2.1 LED’s Table 27-1. LED Outputs DC Parameters Symbol Parameter I Output Low Current, P3.6 and P3.7 LED modes OL Note -20°C to +50° ...

  • Page 164

    Symbol V REF IHZ 27.4 AC Parameters 27.4.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other ...

  • Page 165

    External Program Memory Characteristics Table 27-2. Symbol T T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ Table 27-3. 4337K–USB–04/08 Symbol Description Parameter Oscillator Clock Period ...

  • Page 166

    Table 27-4. Symbol 27.4.3 External Program Memory Read Cycle T ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 AT89C5130A/31A-M 166 AC Parameters for a Variable Clock Standard Type Clock T Min LHLL T ...

  • Page 167

    External Data Memory Characteristics Table 27-5. Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLWL T AVWL T QVWX T QVWH T WHQX T RLAZ T WHLH Table 27-6. 4337K–USB–04/08 Symbol ...

  • Page 168

    Table 27-7. Symbol 27.4.5 External Data Memory Write Cycle ALE PSEN WR PORT 0 PORT 2 AT89C5130A/31A-M 168 AC Parameters for a Variable Clock Standard Type Clock T Min RLRH T Min ...

  • Page 169

    External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 27.4.7 Serial Port Timing - Shift Register Mode Table 27-8. Table 27-9. Table 27-10. AC Parameters for a Variable Clock 4337K–USB–04/08 T LLDV T ...

  • Page 170

    Shift Register Timing Waveform 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 27.4.9 External Clock Drive Characteristics (XTAL1) Table 27-11. AC Parameters Symbol T CLCL T CHCX T CLCX T CLCH T ...

  • Page 171

    Clock Waveforms Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE ...

  • Page 172

    Flash EEPROM Memory and Data EEPROM Memory Table 27-12. Timing Symbol Definitions S (Hardware Condition Table 27-13. Memory AC Timing Symbol T SVRL T RLSX T BHBL T BHBL Figure 27-5. Flash Memory - ISP Waveforms Figure ...

  • Page 173

    USB AC Parameters V CRS Differential Data Lines Table 27-14. USB AC Parameters Symbol FDRATE V CRS t DJ1 t DJ2 t JR1 t JR2 27.6 SPI Interface AC Parameters 27.6.0.1 Definition of Symbols ...

  • Page 174

    V = 2 Symbol T CHCH T CHCX T CLCX SLCH SLCL IVCL IVCH CLIX CHIX T T CLOV, CHOV CLOX CHOX T ...

  • Page 175

    Waveforms Figure 27-7. SPI Slave Waveforms (CPHA= 0) (input) (CPOL= 0) (input) (CPOL= 1) (input) MISO (output) MOSI (input) Note: Figure 27-8. SPI Slave Waveforms (CPHA= 1) (input) SCK (CPOL= 0) (input) SCK (CPOL= 1) (input) MISO (output) MOSI ...

  • Page 176

    Figure 27-9. SPI Master Waveforms (SSCPHA (output) SCK (CPOL= 0) (output) SCK (CPOL= 1) (output) MOSI (input) MISO (output) Note: Figure 27-10. SPI Master Waveforms (SSCPHA (output) SCK (CPOL= 0) (output) SCK (CPOL= 1) (output) MOSI ...

  • Page 177

    ... Ordering Information Table 28-1. Possible Order Entries Part Number Memory Size (Kbytes) AT89C5130A-RDTUM AT89C5130A-PUTUM AT89C5130A-S3SUM AT89C5131A-RDTUM AT89C5131A-PUTUM AT89C5131A-S3SUM Notes: 1. Optional Packing and Package options (please consult Atmel sales representative) -Tape and Reel -Die form 4337K–USB–04/08 Supply Voltage 16 2.7 to 5.5V 16 2.7 to 5.5V 16 2 ...

  • Page 178

    Packaging Information 29.1 64-lead VQFP AT89C5130A/31A-M 178 4337K–USB–04/08 ...

  • Page 179

    STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M - 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT ...

  • Page 180

    PLCC STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT ...

  • Page 181

    QFN 4337K–USB–04/08 AT89C5130A/31A-M 181 ...

  • Page 182

    AT89C5130A/31A-M 182 4337K–USB–04/08 ...

  • Page 183

    Datasheet Revision History 30.1 Changes from 4337F to 4337G 1. Added warning regarding hardware conditions on startup, see 30.2 Changes from 4337G to 4337H 1. Hardware Conditions section Page 46 changed to recommend the use of 1K pull-up between ...

  • Page 184

    Description ............................................................................................... 2 2 Block Diagram .......................................................................................... 3 3 Pinout Description ................................................................................... 4 3.1 Pinout ................................................................................................................4 3.2 Signals ...............................................................................................................6 4 Typical Application ................................................................................ 12 4.1 Recommended External components .............................................................12 4.2 PCB Recommandations ..................................................................................13 5 Clock Controller ..................................................................................... 14 5.1 ...

  • Page 185

    Programming ...................................................................................................43 10.4 Read Data .......................................................................................................43 10.5 Registers .........................................................................................................44 11 In-System Programming (ISP) .............................................................. 45 11.1 Flash Programming and Erasure .....................................................................45 11.2 Boot Process ...................................................................................................46 11.3 Application-Programming-Interface .................................................................47 11.4 XROW Bytes ...................................................................................................47 11.5 Hardware Conditions .......................................................................................48 12 On-chip Expanded ...

  • Page 186

    Serial Peripheral Interface (SPI) ............................................................ 93 19.1 Features ..........................................................................................................93 19.2 Signal Description ............................................................................................93 19.3 Functional Description .....................................................................................95 20 Two Wire Interface (TWI) ..................................................................... 102 20.1 Description .....................................................................................................104 20.2 Notes .............................................................................................................107 20.3 Registers .......................................................................................................118 21 USB Controller ..................................................................................... 120 21.1 ...

  • Page 187

    Electrical Characteristics .................................................................... 161 27.1 Absolute Maximum Ratings ..........................................................................161 27.2 DC Parameters ..............................................................................................161 27.3 USB DC Parameters .....................................................................................163 27.4 AC Parameters ..............................................................................................164 27.5 USB AC Parameters ......................................................................................173 27.6 SPI Interface AC Parameters ........................................................................173 28 Ordering Information ........................................................................... 177 29 ...

  • Page 188

    ... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...