AT89C5131A-M Atmel Corporation, AT89C5131A-M Datasheet - Page 105

• Manufacturer Part Number: AT89C5131A-M
• Manufacturer: Atmel Corporation

Specifications of AT89C5131A-M

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

20.1.1
20.1.2
4337K–USB–04/08
Master Transmitter Mode
Master Receiver Mode
R
W
A:
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P
In Figure 20-4 to Figure 20-7, circles are used to indicate when the serial interrupt flag is set.
The numbers in the circles show the status code held in SSCS. At these points, a service routine
must be executed to continue or complete the serial transfer. These service routines are not crit-
ical since the serial transfer is suspended until the serial interrupt flag is cleared by software.
When the serial interrupt routine is entered, the status code in SSCS is used to branch to the
appropriate service routine. For each status code, the required software action and details of the
following serial transfer are given in Table to Table 20-9.
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(Figure 20-4). Before the master transmitter mode can be entered, SSCON must be initialised as
follows:
Table 20-1.
CR0, CR1 and CR2 define the internal serial bit rate if external bit rate generator is not used.
SSIE must be set to enable TWI. STA, STO and SI must be cleared.
The master transmitter mode may now be entered by setting the STA bit. The 2-wire logic will
now test the 2-wire bus and generate a START condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SI bit in SSCON) is set, and the
status code in SSCS will be 08h. This status must be used to vector to an interrupt routine that
loads SSDAT with the slave address and the data direction bit (SLA+W).
When the slave address and the direction bit have been transmitted and an acknowledgement
bit has been received, SI is set again and a number of status code in SSCS are possible. There
are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was
enabled (AA=logic 1). The appropriate action to be taken for each of these status code is
detailed in Table . This scheme is repeated until a STOP condition is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to
Table 11. After a repeated START condition (state 10h) the TWI module may switch to the mas-
ter receiver mode by loading SSDAT with SLA+R.
In the master receiver mode, a number of data bytes are received from a slave transmitter
(Figure 20-5). The transfer is initialized as in the master transmitter mode. When the START
condition has been transmitted, the interrupt routine must load SSDAT with the 7-bit slave
bit rate
CR2
: Read bit (high level at SDA)
: Write bit (low level at SDA)
Acknowledge bit (low level at SDA)
: STOP condition
SSCON Initialization
SSIE
1
STA
0
STO
0
SI
0
AT89C5130A/31A-M
AA
X
bit rate
CR1
bit rate
CR0
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