AT89C5131A-M Atmel Corporation, AT89C5131A-M Datasheet - Page 122

• Manufacturer Part Number: AT89C5131A-M
• Manufacturer: Atmel Corporation

Specifications of AT89C5131A-M

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

Figure 21-3. UFI Block Diagram
Figure 21-4. Minimum Intervention from the USB Device Firmware
21.2
21.2.1
122
Configuration
AT89C5130A/31A-M
HOST
UFI
C51
IN Transactions:
HOST
UFI
C51
General Configuration
OUT Transactions:
DPLL
SIE
OUT DATA0 (n bytes)
IN
Endpoint FIFO write
NACK
• USB controller enable
• Set address
Before any USB transaction, the 48 MHz required by the USB controller must be correctly
generated (See “Clock Controller” on page 14.).
The USB controller will be then enabled by setting the EUSB bit in the USBCON register.
After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the
USBADDR register. This action will allow the USB controller to answer to the requests sent
at the address 0.
When a SET_ADDRESS request has been received, the USB controller must only answer
to the address defined by the request. The new address will be stored in the USBADDR reg-
ister. The FEN bit and the FADDEN bit in the USBCON register will be set to allow the USB
controller to answer only to requests sent at the new address.
FIU
DPR Control
USB Side
Transfer
Control
FSM
ACK
Asynchronous Information
Transfer
IN
interrupt C51
User DPRAM
DATA1
Endpoint FIFO read (n bytes)
OUT
Endpoint 6
Endpoint 5
Endpoint 4
Endpoint 3
Endpoint 2
Endpoint 1
Endpoint 0
DATA1
IN
NACK
CSREG 0 to 7
DPR Control
mP side
DATA1
Registers
Bank
OUT
ACK
interrupt C51
DATA1
C51
Microcontroller
Interface
Up to 48 MHz
UC_sysclk
Endpoint FIFO write
ACK
4337K–USB–04/08