AT89C5131A-M Atmel Corporation, AT89C5131A-M Datasheet - Page 16

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AT89C5131A-M

Manufacturer Part Number
AT89C5131A-M
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C5131A-M

Flash (kbytes)
32 Kbytes
Max. Operating Frequency
48 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
1024
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART/USB
Watchdog
Yes
5.3.2
5.3.3
16
AT89C5130A/31A-M
PLL Programming
Divider Values
Figure 5-4.
The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF.
The PLL is programmed using the flow shown in Figure 5-5. As soon as clock generation is
enabled user must wait until the lock indicator is set to ensure the clock output is stable.
Figure 5-5.
To generate a 48 MHz clock using the PLL, the divider values have to be configured following
the oscillator frequency. The typical divider values are shown in
Table 5-1.
Oscillator Frequency
PLL Filter Connection
PLL Programming Flow
Typical Divider Values
12 MHz
16 MHz
18 MHz
20 MHz
24 MHz
3 MHz
6 MHz
8 MHz
PLLF
Configure Dividers
Programming
PLL Locked?
N3:0 = xxxxb
R3:0 = xxxxb
LOCK = 1?
Enable PLL
PLLEN = 1
R+1
16
12
8
6
4
3
8
2
PLL
VSS
R
C1
VSS
C2
N+1
1
1
1
1
1
3
5
1
Table
5-1.
PLLDIV
B4h
F0h
70h
50h
30h
20h
72h
10h
4337K–USB–04/08

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