AT89C51CC03 Atmel Corporation, AT89C51CC03 Datasheet
AT89C51CC03
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AT89C51CC03 Summary of contents
Page 1
... Programmable Link to On-chip Timer for Time Stamping and Network Synchronization – Independent Baud Rate Prescaler – Data, Remote, Error and Overload Frame Handling 1. At BRP = 1 sampling point will be fixed. (1) Crystal Frequency in X2 Mode Enhanced 8-bit MCU with CAN Controller and Flash Memory AT89C51CC03 Rev. 4182O–CAN–09/08 ...
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... RD WR AT89C51CC03 2 The AT89C51CC03 is a member of the family of 8-bit microcontrollers dedicated to CAN network applications mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller AT89C51CC03 provides 64K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 2048 byte ERAM ...
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... P3.3/INT1 15 P3.4/T0 16 P3.5/ P1.4/AN4/CEX1 1 P1.5/AN5/CEX2 2 P1.6/AN6/CEX3 3 P1.7/AN7/CEX4 VQFP44 P3.0/RxD 6 P3.1/TxD 7 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/ AT89C51CC03 39 ALE 38 PSEN 37 P0.7/AD7 36 P0.6/AD6 35 P0.5/AD5 34 P0.4/AD4 33 P0.3/AD3 32 P0.2/AD2 31 P0.1/AD1 30 P0.0/AD0 29 P2.0/ ALE 33 32 PSEN 31 P0.7/AD7 30 P0.6/AD6 29 P0.5/AD5 28 P0.4 /AD4 27 P0 ...
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... AT89C51CC03 P1.4/AN4/CEX1 8 P1.5/AN5/CEX2 9 P1.6/AN6/CEX3 10 P1.7/AN7/CEX4 PLCC52 P3.0/RxD 14 P4.3/SCK 15 16 P3.1/TxD P3.2/INT0 17 P3.3/INT1 18 P3.4/T0 19 P3.5/T1/ TESTI must be connected to VSS P1.4/AN4/CEX1 P1.5/AN5/CEX2 3 P1.6/AN6/CEX3 4 P1.7/AN7/CEX4 VQFP64 P3.0/RxD 10 P4.3/SCK 11 P3.1/TxD 12 P3.2/INT0 13 P3 ...
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... In this application, it uses strong internal pull-ups when emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register. It also receives high-order addresses and control signals during program validation. It can drive CMOS inputs without external pull-ups. 4182O–CAN–09/08 AT89C51CC03 5 ...
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... Receiver input of CAN controller. P4.2/MISO: Master Input Slave Output of SPI controller P4.3/SCK: Serial Clock of SPI controller P4.4/MOSI: Master Ouput Slave Input of SPI controller It can drive CMOS inputs without external pull-ups. AT89C51CC03 6 , see section "Electrical Characteristic") because of the internal pull-ups. IL 4182O–CAN–09/08 ...
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... I When External Access is held at the high level, instructions are fetched from the internal Flash. When held at the low level, AT89C51CC03 fetches all instructions from the external program memory XTAL1: Input of the inverting oscillator amplifier and input of the internal clock generator circuits. ...
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... Port 0 and Port 2 AT89C51CC03 8 Figure 1. Port 1, Port 3 and Port 4 Structure READ LATCH INTERNAL D P1.X Q BUS P3.X P4.X WRITE LATCH CL TO LATCH READ PIN Note: The internal pull-up can be disabled on P1 when analog function is selected. Ports 0 and 2 are used for general-purpose I the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups ...
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... CLR Px.y clear bit y of Port x SET Px.y set bit y of Port not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and AT89C51CC03 VDD INTERNAL PULL-UP ( Example ...
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... Quasi-Bidirectional Port Operation AT89C51CC03 10 write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’ ...
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... CDh byte Timer/Counter 2 Low TL2 CCh byte Timer/Counter 0 and TCON 88h 1 control Timer/Counter 0 and TMOD 89h 1 Modes 4182O–CAN–09/08 The Special Function Registers (SFRs) of the AT89C51CC03 fall into the following categories – – – – – – – ...
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... PCA Compare Capture Module 0 L CCAP1L EBh PCA Compare Capture Module 1 L CCAP2L ECh PCA Compare Capture Module 2 L CCAP3L EDh PCA Compare Capture Module 3 L CCAP4L EEh PCA Compare Capture Module 4 L AT89C51CC03 TF2 EXF2 RCLK TCLK – – – – ...
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... BRP5 BRP4 – SJW1 SJW0 – PHS22 PHS21 – ENCH14 ENCH13 ENCH12 ENCH7 ENCH6 ENCH5 – – ENRX – IECH14 IECH13 AT89C51CC03 ET1 EX1 – ESPI ETIM PS PT1 PX1 PSH PT1H PX1H – SPIL POVRL – SPIH POVRH ...
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... CAN Identifier Tag byte 1(PartB) CAN Identifier Tag byte 2 (PartA) CANIDT2 BDh CAN Identifier Tag byte 2 (PartB) CAN Identifier Tag byte 3(PartA) CANIDT3 BEh CAN Identifier Tag byte 3(PartB) AT89C51CC03 IECH7 IECH6 IECH5 – SIT14 SIT13 SIT7 SIT6 SIT5 ...
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... SMOD1 SMOD0 – DPU VPFDP M0 – – ENBOOT CANX2 WDX2 PCAX2 - - - FPL3 FPL2 FPL1 EEPL3 EEPL2 EEPL1 - - - AT89C51CC03 – – RTRTAG IDT1 IDT0 IDMSK7 IDMSK6 IDMSK5 IDMSK25 IDMSK24 IDMSK23 – – – IDMSK17 IDMSK16 IDMSK15 – – – IDMSK9 IDMSK8 IDMSK7 – ...
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... Reserved Note not read or write Reserved Registers 2. These registers are bit addressable. – Sixteen addresses in the SFR space are both byte whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF. AT89C51CC03 16 2/A 3/B 4/C CCAP0H CCAP1H CCAP2H 0000 0000 ...
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... Clock Description 4182O–CAN–09/08 The AT89C51CC03 core needs only 6 clock periods per machine cycle. This feature, called”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • ...
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... Figure 5. Clock CPU Generation Diagram Hardware byte CKCON.0 XTAL1 XTAL2 PD PCON.1 ÷ 2 ÷ CKCON.0 SPIX2 CANX2 CKCON0.7 CKCON1.0 AT89C51CC03 18 X2B PCON.0 On RESET IDL X2 ÷ ÷ 2 ÷ ÷ ÷ WDX2 PCAX2 SIX2 CKCON0.6 CKCON0.5 CKCON0.4 CKCON0 ...
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... For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate. 4182O–CAN–09/08 AT89C51CC03 X2 Mode STD Mode 19 ...
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... Registers AT89C51CC03 20 Table 2. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register CANX2 WDX2 PCAX2 Bit Bit Number Mnemonic Description (1) CAN clock 7 CANX2 Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. WatchDog clock 6 WDX2 Clear to select 6 clock periods per peripheral clock cycle ...
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... Clear to select 6 clock periods per peripheral clock cycle. 0 SPIX2 Set to select 12 clock periods per peripheral clock cycle. Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = 0000 0000b AT89C51CC03 SPIX2 21 ...
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... Data Memory AT89C51CC03 22 The AT89C51CC03 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded 2048 Bytes RAM segment (ERAM). ...
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... Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly. AT89C51CC03 Description Register bank 0 from 00h to 07h Register bank 0 from 08h to 0Fh ...
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... WR# O Write signal output to external memory. This section describes the bus cycles the AT89C51CC03 executes to read (see Figure 11), and write data (see Figure 12) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor- mation on X2 mode ...
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... RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. Figure 12. External Data Write Waveforms CPU Clock ALE WR#1 P0 DPL Notes: 1. WR# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. AT89C51CC03 D7:0 DPH or P22 D7:0 DPH or P22 25 ...
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... Application AT89C51CC03 26 The AT89C51CC03 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 8) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 13) ...
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... The value read from these bits are indeterminate. Do not set this bit. Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0 Pulse length in clock period AT89C51CC03 RS1 RS0 XRS2 XRS1 XRS0 ...
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... AT89C51CC03 28 Bit Bit Number Mnemonic Description ERAM size: Accessible size of the ERAM XRS 2:0 ERAM size 000 256 Bytes 001 512 Bytes 010 768 Bytes 4-2 XRS1-0 011 1024 Bytes 100 1792 Bytes 101 2048 Bytes (default configuration after reset) 110 Reserved 111 ...
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... This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51CC03 is powered up. In order to startup and maintain the microcontroller in correct operating mode stabilized in the V ...
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... Figure 15. Power Fail Detect Vcc Reset Vcc AT89C51CC03 30 When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 lev- els are above and below VIH and VIL ...
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... Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C51CC03 datasheet. The status of the Port pins during reset is detailed in Table 9. Figure 17. Reset Circuitry and Power-On Reset RST VSS a ...
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... RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit kΩ resis- tor must be added as shown Figure 18. Figure 18. Recommended Reset Output Schematic VDD + RST VDD 1K RST VSS AT89C51CC03 To other on-board circuitry 4182O–CAN–09/08 ...
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... Idle mode. The contents of the status of the Port pins during Idle mode is detailed in Table 9. To enter Idle mode, set the IDL bit in PCON register (see Table 10). The AT89C51CC03 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed ...
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... OSC Active phase AT89C51CC03 34 To enter Power-Down mode, set PD bit in PCON register. The AT89C51CC03 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is restored to the normal operating level ...
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... Data Data code) Idle (external Floating Data code) Power- Down(inter Data Data nal code) Power- Down Floating Data (external code) AT89C51CC03 Port 2 Port 3 Port 4 High High High Data Data Data Data Data Data Data Data Data Data Data Data ALE ...
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... Registers AT89C51CC03 36 Table 10. PCON Register PCON (S87:h) Power configuration Register Bit Bit Number Mnemonic Description Reserved 7-4 - The value read from these bits is indeterminate. Do not set these bits. General Purpose flag 1 3 GF1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode ...
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... The following procedure is used to read the data stored in the EEPROM memory: • Save and disable interrupt • Set bit EEE of EECON register • Load DPTR with the address to read • Execute a MOVX A, @DPTR • Restore interrupt AT89C51CC03 37 ...
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... Examples AT89C51CC03 38 ;*F*************************************************************************;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ret ;*F************************************************************************* ...
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... Clear to map the XRAM space during MOVX. Programming Busy flag Set by hardware when programming is in progress. 0 EEBUSY Cleared by hardware when programming is done. Can not be set or cleared by software. Reset Value = XXXX XX00b Not bit addressable AT89C51CC03 EEPL0 - - 1 0 EEE EEBUSY ...
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... Program/Code Memory AT89C51CC03 40 The AT89C51CC03 implement 64K Bytes of on-chip program/code memory. Figure 20 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical era- sure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD volt- age ...
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... This signal is active low during external code fetch or external code read (MOVC instruction). This section describes the bus cycles the AT89C51CC03 executes to fetch code (see Figure 22) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor- mation on X2 mode see section “ ...
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... Extra Row (128 Bytes) Column Latches (128 Bytes) AT89C51CC03 42 PCL D7:0 PCH AT89C51CC03 features two on-chip Flash memories: • Flash memory FM0: containing 64K Bytes of program memory (user space) organized into 128 byte pages, • Flash memory FM1: 2K Bytes for boot loader and Application Programming Interfaces (API). ...
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... Extra Row (128 Bytes) Column Latches (128 Bytes) 4182O–CAN–09/08 FFFFh 64K Bytes F800h FM0 0000h Memory space not accessible AT89C51CC03 FFFFh 2K Bytes Flash memory boot space FM1 F800h FM1 mapped between FFFFh and F800h when bit ENBOOT is set in AUXR1 register ...
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... FM0 Memory Architecture User Space Extra Row (XRow) Hardware security Byte (HSB) Column Latches Cross Flash Memory Access Description AT89C51CC03 44 The Flash memory is made blocks (see Figure 23): • The memory array (user space) 64K Bytes • The Extra Row • ...
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... Action Read Load column latch FM0 (user Flash) Write Read Load column latch FM1 (boot Flash) Write Read External Load column latch memory Write (a) Depend upon general lock bit configuration. AT89C51CC03 FM0 FM1 (user Flash) (boot Flash (a) ...
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... Overview of FM0 Operations Flash Registers (SFR) FCON Register AT89C51CC03 46 The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the column latches, HSB, extra row and EEDATA in the working data or code space. ...
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... Notes: 1. The column latches reset is a new option introduced in the AT89C51CC03, and is not available in T89C51CC01/2 FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5xh followed by Axh. Table 16 summarizes the memory spaces to program according to FMOD1:0 bits ...
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... Status of the Flash Memory Selecting FM1 Loading the Column Latches AT89C51CC03 48 Table 16. Programming Spaces Write to FCON FPL3:0 FPS User Extra Row Hardware 5 X Security A X Byte Reset 5 X Columns A X Latches Notes: 1. The sequence 5xh and Axh must be executing without instructions between them otherwise the programming is not executed (see Flash Status Register) 2 ...
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... Load the DPTR with the address to load. • Load Accumulator register with the data to load. • Execute the MOVX @DPTR, A instruction. • If needed loop the three last instructions until the page is completely loaded. • unmap the column latch. • Restore Interrupt AT89C51CC03 49 ...
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... Programming the Flash Spaces User Extra Row AT89C51CC03 50 Figure 25. Column Latches Loading Procedure Note: The last page address used when loading the column latch is the one used to select the page programming address. The following procedure is used to program the User space and is summarized in Figure 26: • ...
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... Launch the programming by writing the data sequence 54h followed by A4h in FCON register (only from FM1). The end of the programming indicated by the FBusy flag cleared. • Restore the interrupts. AT89C51CC03 Flash Spaces Programming Column Latches Loading see Figure 25 Save and Disable IT ...
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... Reset the Column Latches Error Reports Flash Programming Sequence Errors AT89C51CC03 52 Figure 27. Hardware Programming Procedure Flash Spaces Programming Save and Disable FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, A End Loading Restore IT An automatic reset of the column latches is performed after a successful Flash write sequence ...
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... The three lock bits in Hardware Security Byte (see "In-System Programming" section) are programmed according to Table 17 provide different level of protection for the on- chip code and data located in FM0 and FM1. The only way to write this bits are the parallel mode. They are set by default to level 4 AT89C51CC03 Security FCON= 00000xx0b Data Read ...
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... AT89C51CC03 54 Table 17. Program Lock Bit Program Lock Bits Security LB0 LB1 LB2 level Protection Description program lock features enabled. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory sampled and latched on reset, and further parallel programming of the Flash is disabled ...
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... Boot Flash • Flash Column latch The table below provide the different kind of memory which can be accessed from differ- ent code location. XRAM ERAM Boot FLASH (idle AT89C51CC03 Hardware FM0 E² Data Byte (1) (1) ( ...
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... Sharing Instructions AT89C51CC03 56 Table 19. Instructions shared XRAM EEPROM Action RAM ERAM DATA Read MOV MOVX MOVX Write MOV MOVX MOVX Note using Column Latch Table 20. Read MOVX A, @DPTR EEE bit in FPS in EECON Register FCON Register ENBOOT Table 21. Write MOVX @DPTR,A ...
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... F800h to FFFFh 0000h to 007h X (2) See 000h to FFFFh AT89C51CC03 Hardware FM1 FM0 XROW not use this configuration not use this configuration External Byte Code ...
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... With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the AT89C51CC03 allows the system engineer the development of applica- tions with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • ...
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... PSEN after the fall- ing edge of Reset is signaled. The hardware conditions are sampled at reset signal Falling Edge, thus they can be released at any time when reset input is low ensure correct microcontroller startup, the PSEN pin should not be tied to ground during power-on. AT89C51CC03 59 ...
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... Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All these APIs are describe in an documentation: "In-System Programing: Flash Library for AT89C51CC03" available on the Atmel web site. Table 23. XROW Mapping Description Copy of the Manufacturer Code ...
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... Lock Bits After erasing the chip in parallel mode, the default value is : FFh The erasing in ISP mode (from bootloader) does not modify this byte. Notes: 1. Only the 4 MSB bits can be accessed by software. 2. The 4 LSB bits can only be accessed by parallel mode. AT89C51CC03 ...
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... Figure 32. Framing Error Block Diagram AT89C51CC03 62 The AT89C51CC03 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously ...
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... To support automatic address recognition, a device is identified by a given address and a broadcast address. Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). AT89C51CC03 ...
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... Given Address Broadcast Address AT89C51CC03 64 Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time ...
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... Receive Interrupt flag Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0, see Figure 33. and Figure 34. in the other modes. Reset Value = 0000 0000b Bit addressable AT89C51CC03 REN TB8 RB8 Mode Baud Rate ...
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... AT89C51CC03 66 Table 26. SADEN Register SADEN (S:B9h) Slave Address Mask Register – – – Bit Bit Number Mnemonic Description 7-0 Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 27. SADDR Register SADDR (S:A9h) Slave Address Register – ...
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... Power-Down mode bit 1 PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit 0 IDL Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable AT89C51CC03 POF GF1 GF0 IDL 67 ...
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... Timer 0 AT89C51CC03 68 The AT89C51CC03 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. ...
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... TRx TCON reg Mode 1 configures Timer 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 36). The selected input increments TL0 register. 0 THx (8 bits) 1 TRx TCON reg AT89C51CC03 Timer x TLx Overflow Interrupt TFx (5 bits) Request TCON reg Timer x TLx ...
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... FTx ÷ 6 CLOCK See the “Clock” section AT89C51CC03 70 Mode 2 configures Timer 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 37). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0 ...
Page 71
... TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer mode 3. AT89C51CC03 71 ...
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... Interrupt Registers AT89C51CC03 72 Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting interrupts are globally enabled by setting EA bit in IEN0 register. ...
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... TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits. 1. Reloaded from TH1 at overflow. 2. Reloaded from TH0 at overflow. Reset Value = 0000 0000b AT89C51CC03 M01 GATE0 C/T0# Operating mode Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). Mode 1: 16-bit Timer/Counter. ...
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... AT89C51CC03 74 Table 32. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register – – – Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0. Reset Value = 0000 0000b Table 33. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register – – – Bit Bit ...
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... Table 35. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register – – – Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1. Reset Value = 0000 0000b AT89C51CC03 – – – – 0 – 75 ...
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... T2 AT89C51CC03 76 The AT89C51CC03 timer 2 is compatible with timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected controlled by T2CON register (See Table ) and T2MOD register (See Table 38). Timer 2 operation is similar to Timer 0 and Timer 1 ...
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... It is possible to use timer baud rate generator and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. TR2 T2CON.2 Toggle EXEN2 T2CON reg AT89C51CC03 FT2clock ---------------------------------------------------------------------------------------- - = × ( ⁄ 4 65536 RCAP2H – RCAP2L ...
Page 78
... Registers AT89C51CC03 78 Table 36. T2CON Register T2CON (S:C8h) Timer 2 Control Register TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...
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... Set to enable timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable Table 38. TH2 Register TH2 (S:CDh) Timer 2 High Byte Register Bit Bit Number Mnemonic Description 7-0 High Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable AT89C51CC03 T2OE DCEN 0 ...
Page 80
... AT89C51CC03 80 Table 39. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register Bit Bit Number Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 40. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register Bit Bit Number Mnemonic Description 7-0 High Byte of Timer 2 Reload/Capture ...
Page 81
... Fwd Clock - 4182O–CAN–09/08 AT89C51CC03 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz in X1 mode. ...
Page 82
... Watchdog Programming AT89C51CC03 82 The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 42. Machine Cycle Count compute WD Time-Out, the following formula is applied: ---------------------------------------------------------------------------- - FTime Out – = WDX2 × ...
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... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting AT89C51CC03 while in Idle mode, the user should always set up a timer that will period- ically exit Idle, service the WDT, and re-enter Idle mode. ...
Page 84
... AT89C51CC03 84 Table 45. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register – – – Bit Bit Number Mnemonic Description 7 - Watchdog Control Value Reset Value = 1111 1111b Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences. ...
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... Transmission Request (RTR)" bit used to distinguish between the data frame and the data request frame called remote frame. The following "Control field" contains the "IDen- tifier Extension (IDE)" bit and the "Data Length Code (DLC)" used to indicate the AT89C51CC03 1 Crystal frequency in X2 mode. ...
Page 86
... Field Format Co-existence Bit Timing Bit Construction AT89C51CC03 86 number of following data bytes in the "Data field" remote frame, the DLC contains the number of requested data bytes. The "Data field" that follows can hold data bytes. The frame integrity is guaranteed by the following "Cyclic Redundant Check (CRC)" ...
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... If, for example, the transmitter oscillator is slower than the receiver oscillator, the next falling edge used for resynchronization may be delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and the end of the bit time. AT89C51CC03 Nominal CAN Bit Time PHASE_SEG_1 PHASE_SEG_2 ...
Page 88
... Programming the Sample Point Arbitration Errors Error at Message Level AT89C51CC03 88 If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in order to adjust the sample point for bit N+1 and the end of the bit time The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resynchronization Jump Width ...
Page 89
... The programmable 16-bit Timer (CANTIMER) is used to stamp each received and sent message in the CANSTMP register. This timer starts counting as soon as the CAN con- troller is enabled by the ENA bit in the CANGCON register. The Time Trigger Communication (TTC) protocol is supported by the AT89C51CC03. AT89C51CC03 89 ...
Page 90
... Figure 47. CAN Controller Block Diagram TxDC RxDC CAN Controller Mailbox and Registers Organization AT89C51CC03 90 Bit Error Timing Counter Logic Rec/Tec Page DPR(Mailbox + Registers) Register µC-Core Interface Interface Core Bus Control The pagination allows management of the 321 registers including 300(15x20) Bytes of mailbox via 34 SFR’ ...
Page 91
... Ch Tag - 2 Ch Tag - 3 Ch Tag - 4 Ch Mask Mask Mask Mask - 4 Ch.0 TimStmp High Ch.0 TimStmp Low AT89C51CC03 message object 14 - Status message object 14 - Control and DLC Ch.14 - Message Data - byte 0 Ch. Tag - 1 Ch. Tag - 2 Ch. Tag - 3 Ch. Tag - 4 Ch. Mask - 1 Ch. Mask - 2 Ch ...
Page 92
... Working on Message Objects CAN Controller Management AT89C51CC03 92 The Page message object register (CANPAGE) is used to select one of the 15 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected message object number in the corresponding SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is managed by the Page message object register with an auto-incrementation at the end of each access ...
Page 93
... The frames following the buffer-full interrupt will not stored and no status will be over- written in the CANSTCH registers involved in the buffer until at least one of the buffer message objects is re-enabled in reception. This flag must be cleared by the software in order to acknowledge the interrupt. AT89C51CC03 Block buffer buffer 7 buffer 6 ...
Page 94
... CANGIT.4 SERG CANGIT.3 CERG CANGIT.2 FERG CANGIT.1 AERG CANGIT.0 OVRTIM CANGIT.5 AT89C51CC03 94 The different interrupts are: • Transmission interrupt, • Reception interrupt, • Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error), • Interrupt when Buffer receive is full, • ...
Page 95
... When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised. Consequently, two consecutive interrupts can occur, both due to the same error. When a message object error occurs and is set in CANSTCH register, no general error are set in CANGIE register. AT89C51CC03 95 ...
Page 96
... Figure 51. Sample And Transmission Point FCAN Prescaler BRP CLOCK AT89C51CC03 96 FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s. Field and segment abbreviations: • ...
Page 97
... If we chose a sample point at 66.6% => Tphs2 = 4TQ => PHS2 = 3 Tbit = Tphs1 + Tprs, let us choose Tprs = 3 Tphs1 = 4 PHS1 = 3 and PRS = 2 BRP = 0 so CANBT1 = 00h SJW = 0 and PRS = 2 so CANBT2 = 04h PHS2 = 3 and PHS1 = 3 so CANBT3 = 36h AT89C51CC03 Tphs2 (2) Tphs1 (1) Tphs2 - Tsjw (4) Sample Point Transmission Point ...
Page 98
... Fault Confinement ERRP = 1 BOFF = 0 AT89C51CC03 98 With respect to fault confinement, a unit may be in one of the three following status: • error active • error passive • bus off An error active unit takes part in bus communication and can send an active error frame when the CAN macro detects an error. ...
Page 99
... Rx Shift Register (internal) ID and RB 13/32 Write Enable 13/32 ID TAG Registers (Ch i) and CanConch ID and RB example: To accept only ID = 318h in part A. ID MSK = 111 1111 1111 b ID TAG = 011 0001 1000 b CAN SFRs AT89C51CC03 RTR IDE 13/ 13/32 13/32 ID MSK Registers ( and RB RTR IDE Hit (Ch i) ...
Page 100
... CAN controller message object disabled 1 message object in u transmission message object disabled 0 c message object in 0 reception by user c AT89C51CC03 100 Description of the different steps for: • Data Frame Node A Node ...
Page 101
... RXOK i CANSTCH.5 CANSTMPH and CANSTMPL 4182O–CAN–09/08 The AT89C51CC03 has a programmable 16-bit Timer (CANTIMH and CANTIML) for message stamp and TTC. This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANG- CON register. Two modes in the timer are implemented: • ...
Page 102
... CAN Autobaud and Listening Mode Routines Examples AT89C51CC03 102 To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledg- ing the received messages. It cannot send any message. The error flags are updated. ...
Page 103
... Clear the Status register CANSTCH = 00h; // load the identifier to send (ex: 555h) CANIDT1 = AAh; CANIDT2 = A0h; // load data to send CANMSG = 00h CANMSG = 01h CANMSG = 02h CANMSG = 03h CANMSG = 04h CANMSG = 05h CANMSG = 06h CANMSG = 07h // configure the control register CANCONCH = 18h AT89C51CC03 103 ...
Page 104
... AT89C51CC03 104 4. Interrupt routine // Save the current CANPAGE // Find the first message object which generate an interrupt in CANSIT1 and CANSIT2 // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of interrupt is generated // Manage the interrupt // Clear the status register CANSTCH = 00h; ...
Page 105
... CANGIT CANTEC 0x00 0000 0000 0000 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C AT89C51CC03 5/D 6/E 7/F CCAP3H CCAP4H 0000 0000 0000 0000 ADDH ADCF IPH1 0000 0000 0000 0000 xxxx x000 CCAP3L CCAP4L 0000 0000 ...
Page 106
... Registers AT89C51CC03 106 Table 48. CANGCON Register CANGCON (S:ABh) CAN General Control Register ABRQ OVRQ TTC SYNCTTC Bit Number Bit Mnemonic Description Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control 7 ABRQ and DLC register) is done for each message object. The pending transmission communications are immediately aborted but the on-going communication will be terminated normally, setting the appropriate status flags, TXOK or RXOK ...
Page 107
... Because an enable/disable command is not effective immediately, this status 2 ENFG bit gives the true state of a chosen mode. This flag does not generate an interrupt. Bus Off Mode 1 BOFF see Figure 53 Error Passive Mode 0 ERRP see Figure 53 Reset Value = x0x0 0000b AT89C51CC03 TBSY RBSY ENFG BOFF 1 0 ERRP 107 ...
Page 108
... AT89C51CC03 108 Table 50. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt CANIT - OVRTIM Bit Number Bit Mnemonic Description General Interrupt Flag This status bit is the image of all the CAN controller interrupts sent to the 7 CANIT interrupt controller. It can be used in the case of the polling method. ...
Page 109
... Table 52. CANREC Register CANREC (S:9Dh Read Only) CAN Reception Error Counter REC7 REC6 REC5 Bit Number Bit Mnemonic Description Reception Error Counter 7-0 REC7:0 see Figure 53 Reset Value = 00h AT89C51CC03 TEC4 TEC3 TEC2 TEC1 REC4 REC3 REC2 REC1 1 0 TEC0 ...
Page 110
... AT89C51CC03 110 Table 53. CANGIE Register CANGIE (S:C1h) CAN General Interrupt Enable ENRX Bit Number Bit Mnemonic Description Reserved 7-6 - The values read from these bits are indeterminate. Do not set these bits. Enable Receive Interrupt 5 ENRX 0 - Disable 1 - Enable Enable Transmit Interrupt 4 ENTX ...
Page 111
... MOb in disabled mode, applying abortion or standby mode. 7-0 ENCH7 message object disabled: MOb available for a new transmission or reception message object enabled: MOb in use. This bit is resetable by re-writing the CANCONCH of the corresponding message object. Reset Value = 0000 0000b AT89C51CC03 ENCH12 ENCH11 ENCH10 ENCH9 4 ...
Page 112
... AT89C51CC03 112 Table 56. CANSIT1 Register CANSIT1 (S:BAh Read Only) CAN Status Interrupt Message Object Registers SIT14 SIT13 Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set this bit. Status of Interrupt by Message Object interrupt. ...
Page 113
... CAN Enable Interrupt Message Object Registers IECH 7 IECH 6 IECH 5 Bit Number Bit Mnemonic Description Enable interrupt by Message Object 0 - disable IT. 7-0 IECH7 enable IT. IECH7 0000 1100 -> Enable IT’s of message objects 3 and 2. Reset Value = 0000 0000b AT89C51CC03 IECH12 IECH11 IECH10 IECH9 IECH 4 IECH 3 IECH 2 IECH ...
Page 114
... AT89C51CC03 114 Table 60. CANBT1 Register CANBT1 (S:B4h) CAN Bit Timing Registers BRP 5 BRP 4 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Baud rate prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing ...
Page 115
... The value read from this bit is indeterminate. Do not set this bit. Note: The CAN controller bit timing registers must be accessed only if the CAN controller is dis- abled with the ENA bit of the CANGCON register set to 0. See Figure 52. No default value after reset. AT89C51CC03 ...
Page 116
... AT89C51CC03 116 Table 62. CANBT3 Register CANBT3 (S:B6h) CAN Bit Timing Registers PHS2 2 PHS2 1 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Phase Segment 2 This phase is used to compensate for phase edge errors. This segment can be shortened by the re-synchronization jump width ...
Page 117
... Number of Bytes in the data field of the message. The range of DLC is from 3-0 DLC3:0 This value is updated when a frame is received (data or remote frame). If the expected DLC differs from the incoming DLC, a warning appears in the CANSTCH register. No default value after reset AT89C51CC03 CHNB 0 AINC INDX2 4 ...
Page 118
... AT89C51CC03 118 Table 65. CANSTCH Register CANSTCH (S:B2h) CAN Message Object Status Register DLCW TXOK RXOK Bit Number Bit Mnemonic Description Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame 7 DLCW type, the DLC field of the CANCONCH register is updated by the received DLC ...
Page 119
... CANIDT3 for V2.0 part A (S:BEh) CAN Identifier Tag Registers Bit Number Bit Mnemonic Description Reserved 7-0 - The values read from these bits are indeterminate. Do not set these bits. No default value after reset. AT89C51CC03 IDT 7 IDT 6 IDT 5 IDT ...
Page 120
... AT89C51CC03 120 Table 69. CANIDT4 Register for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers Bit Number Bit Mnemonic Description Reserved 7-3 - The values read from these bits are indeterminate. Do not set these bits. 2 RTRTAG Remote Transmission Request Tag Value. ...
Page 121
... CAN Identifier Mask Registers IDMSK 10 IDMSK 9 IDMSK 8 Bit Number Bit Mnemonic Description IDentifier mask value 0 - comparison true forced. 7-0 IDTMSK10 bit comparison enabled. See Figure 54. No default value after reset. AT89C51CC03 IDT 9 IDT 8 IDT IDT 1 IDT 0 RTRTAG RB1TAG ...
Page 122
... AT89C51CC03 122 Table 75. CANIDM2 Register for V2.0 part A CANIDM2 for V2.0 part A (S:C5h) CAN Identifier Mask Registers IDMSK 2 IDMSK 1 IDMSK 0 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison true forced. 7-5 IDTMSK2 bit comparison enabled. See Figure 54. Reserved 4-0 - The values read from these bits are indeterminate. Do not set these bits. ...
Page 123
... IDMSK 28 IDMSK 27 IDMSK 26 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison true forced. 7-0 IDMSK28: bit comparison enabled. See Figure 54. Note: The ID Mask is only used for reception. No default value after reset. AT89C51CC03 RTRMSK IDMSK 25 IDMSK 24 IDMSK 23 IDMSK ...
Page 124
... AT89C51CC03 124 Table 79. CANIDM2 Register for V2.0 part B CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison true forced. 7-0 IDMSK20: bit comparison enabled. See Figure 54. Note: The ID Mask is only used for reception. ...
Page 125
... If auto-incrementation is used, at the end of the data register writing or reading cycle, the mailbox pointer is auto-incremented. The range of the counting is 8 with no end loop (0, 1,..., 7, 0,...) No default value after reset. AT89C51CC03 IDMSK 1 IDMSK 0 ...
Page 126
... AT89C51CC03 126 Table 83. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 Bit Number Bit Mnemonic Description Timer Prescaler of CAN Timer This register is a prescaler for the main timer upper counter 7-0 TPRESC7:0 range = 0 to 255. See Figure 55. ...
Page 127
... CANTTCH (S:A5h Read Only) CAN TTC Timer High TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 Bit Number Bit Mnemonic Description High byte of TTC Timer 7-0 TIMTTC15:8 See Figure 55. Reset Value = 0000 0000b AT89C51CC03 TIMSTMP TIMSTMP TIMSTMP TIMSTMP 9 TIMSTMP ...
Page 128
... AT89C51CC03 128 Table 89. CANTTCL Register CANTTCL (S:A4h Read Only) CAN TTC Timer Low TIMTTC 7 TIMTTC 6 TIMTTC 5 Bit Number Bit Mnemonic Description Low byte of TTC Timer 7-0 TIMTTC7:0 See Figure 55. Reset Value = 0000 0000b TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 4182O–CAN–09/08 ...
Page 129
... Slave obvious that only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port pins (Figure 58). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. AT89C51CC03 Slave 1 Slave 3 Slave 2 ...
Page 130
... Baud Rate AT89C51CC03 130 In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. ...
Page 131
... A serial clock line (SCK) synchronizes shifting and sam- pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities. AT89C51CC03 SPDAT Transmit Data Register Shift Register ...
Page 132
... Master Mode Slave Mode Transmission Formats AT89C51CC03 132 When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 59) ...
Page 133
... This format may be preferred in systems having only one Master and only one Slave driving the MISO data line. For an SPI configured in master or slave mode, a queued data byte must be transmit- ted/received immediately after the previous transmission has completed. AT89C51CC03 ...
Page 134
... MISO Data Byte 1 BYTE 1 under transmission SPTE AT89C51CC03 134 When a transmission is in progress a new data can be queued and sent as soon as transmission has been completed possible to transmit bytes without latency, useful in some applications. The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that the user application can write SPDAT with the data to be transmitted until the SPTE becomes cleared ...
Page 135
... At any time, a ’1’ on the SS pin of a slave SPI puts the MISO pin in a high impedance state and internal state counter is cleared. Also, the slave SPI ignores all incoming SCK clocks, even if it was already in the middle of a transmission. A new transmission will be performed as soon as SS pin returns low. AT89C51CC03 ...
Page 136
... OverRun Condition Interrupts AT89C51CC03 136 Figure 65. Mode Fault Conditions in Slave Mode 0 SCK cycle # 1 SCK z 0 (from master) 1 MOSI z (from master MISO MSB z (from slave (slave) 0 MODF detected Note: when SS is discarded (SS disabled not possible to detect a MODF error in slave mode because the SPI is internally selected ...
Page 137
... Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request is generated Serial Peripheral Master 4 MSTR Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master. AT89C51CC03 SPI CPU Interrupt Request MSTR CPOL ...
Page 138
... Serial Peripheral Status Register and Control (SPSCR) AT89C51CC03 138 Bit Number Bit Mnemonic Description Clock Polarity 3 CPOL Cleared to have the SCK set to ’0’ in idle state. Set to have the SCK set to ’1’ in idle state. Clock Phase Cleared to have the data sampled when the SCK leaves the idle ...
Page 139
... A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register. Table 94. SPDAT Register SPDAT - Serial Peripheral Data Register (0D6H Reset Value = Indeterminate R7:R0: Receive data bits AT89C51CC03 139 ...
Page 140
... AT89C51CC03 140 SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: • Do not change SPR2, SPR1 and SPR0 • Do not change CPHA and CPOL • ...
Page 141
... CPS1 and CPS0 bits in the CMOD SFR (see Table 8) and can be programmed to run at: • 1/6 the PCA clock frequency. • 1/2 the PCA clock frequency. • the Timer 0 overflow. • the input on the ECI pin (P1.2). AT89C51CC03 External I/O Pin P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 141 ...
Page 142
... Figure 67. PCA Timer/Counter FPca/6 FPca/2 T0 OVF P1.2 Idle PCA Modules AT89C51CC03 142 CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which allows the PCA to stop during idle mode. ...
Page 143
... PCA counter registers (CH and CL) into the module’s capture reg- isters (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. AT89C51CC03 CCON To Interrupt ...
Page 144
... CH (8 bits) (8 bits) “0” Reset Write to “1” CCAPnL Write to CCAPnH AT89C51CC03 144 CAPMn ECOMn CAPPn CAPNn MATn 7 CCAPMn Register ( The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set ...
Page 145
... When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated with- out glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode. AT89C51CC03 CCON 0xD8 PCA IT ...
Page 146
... Figure 72. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) PCA WatchDog Timer AT89C51CC03 146 CCAPnH CCAPnL 8-Bit Comparator ECOMn PWMn CCAPMn.6 CCAPMn.1 An on-board WatchDog timer is available with the PCA to improve system reliability without increasing chip count. WatchDog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge ...
Page 147
... The value read from this bit is indeterminate. Do not set this bit. Enable PCA Counter Overflow Interrupt bit 0 ECF Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt. Reset Value = 00XX X000b AT89C51CC03 CPS1 Internal Clock, FPca/6 ...
Page 148
... AT89C51CC03 148 Table 96. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Bit Number Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA 7 CF interrupt request if the ECF bit in CMOD register is set. ...
Page 149
... CCAP4L (S:EEh) PCA Low Byte Compare/Capture Module n Register (n=0.. CCAPnL 7 CCAPnL 6 CCAPnL 5 Bit Bit Number Mnemonic Description CCAPnL 7:0 Low byte of EWC-PCA comparison or capture values 7:0 Reset Value = 0000 0000b AT89C51CC03 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH CCAPnL 4 CCAPnL 3 CCAPnL 2 CCAPnL ...
Page 150
... AT89C51CC03 150 Table 99. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Bit Number Mnemonic Description Reserved 7 - The Value read from this bit is indeterminate. Do not set this bit. Enable Compare Mode Module x bit Clear to disable the Compare function ...
Page 151
... Reset Value = 0000 00000b Table 101. CL Register CL (S:E9h) PCA counter Register Low Value Bit Bit Number Mnemonic Description 7:0 CL0 7:0 Low byte of Timer/Counter Reset Value = 0000 00000b AT89C51CC03 ...
Page 152
... This section describes the on-chip 10 bit analog-to-digital converter of the AT89C51CC03. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit cascaded potentiometric ADC ...
Page 153
... ADCON.0 Figure 74 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the Section “AC Characteristics” of the AT89C51CC03 datasheet. T CONV AT89C51CC03 ADCON ...
Page 154
... ADC Converter Operation Voltage Conversion Clock Selection AT89C51CC03 154 A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set (see Figure 76) ...
Page 155
... Clear the End of conversion flag ADCON and = EFh // read the value value_converted = (ADDH << 2)+(ADDL) 3. Start a precision conversion (need interrupt ADC) // The variable "channel" contains the channel to convert // Enable ADC AT89C51CC03 ADC Clock A/D Converter ADCI EADC IEN1.1 155 ...
Page 156
... AT89C51CC03 156 EADC = 1 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: to enable the ADC interrupt 4182O–CAN–09/08 ...
Page 157
... Set by hardware when ADC result is ready to be read. This flag can generate an 4 ADEOC interrupt. Must be cleared by software. Start and Status 3 ADSST Set to start an A/D conversion. Cleared by hardware after completion of the conversion Selection of Channel to Convert 2-0 SCH2:0 see Table 102 Reset Value =X000 0000b AT89C51CC03 ADEOC ADSST SCH2 1 0 ...
Page 158
... AT89C51CC03 158 Table 105. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Bit Bit Number Mnemonic Description Reserved 7-5 - The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler 4-0 PRS4:0 (1) See Note Reset Value = XXX0 0000b Note mode: For PRS > ...
Page 159
... Bit Bit Number Mnemonic Description Reserved 7-2 - The value read from these bits are indeterminate. Do not set these bits. ADC result 1-0 ADAT1:0 bits 1-0 Reset Value = 00h AT89C51CC03 159 ...
Page 160
... Converter CAN Timer SPI Controller AT89C51CC03 160 The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA, a CAN interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below. ...
Page 161
... Timer0 (TF0) external interrupt (INT1) Timer1 (TF1) PCA (CF or CCFn) UART (RI or TI) Timer2 (TF2) CAN (Txok, Rxok, Err or OvrBuf) ADC (ADCI) CAN Timer Overflow (OVRTIM) SPI interrupt AT89C51CC03 IPL.x Interrupt Level Priority 0 0 (Lowest (Highest) ...
Page 162
... Registers AT89C51CC03 162 Table 110. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. ...
Page 163
... ADC Interrupt Enable bit 1 EADC Clear to disable the ADC interrupt. Set to enable the ADC interrupt. CAN Interrupt Enable bit 0 ECAN Clear to disable the CAN interrupt. Set to enable the CAN interrupt. Reset Value = xxxx 0000b bit addressable AT89C51CC03 ESPI ETIM EADC 0 ECAN 163 ...
Page 164
... AT89C51CC03 164 Table 112. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority bit 6 PPC Refer to PPCH for priority level ...
Page 165
... Refer to PI2CH for priority level. ADC Interrupt Priority Level Less Significant Bit 1 PADCL Refer to PSPIH for priority level. CAN Interrupt Priority Level Less Significant Bit 0 PCANL Refer to PKBH for priority level. Reset Value = XXXX 0000b bit addressable AT89C51CC03 SPIL POVRL PADCL 0 PCANL ...
Page 166
... AT89C51CC03 166 Table 114. IPL0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority Level Most Significant bit PPCH PPC ...
Page 167
... PADCH CAN Interrupt Priority Level Most Significant bit PCANH PCANL Priority level PCANH Reset Value = XXXX 0000b AT89C51CC03 SPIH POVRH PADCH Lowest Highest Lowest Highest Lowest Highest Lowest Highest 1 0 PCANH 167 ...
Page 168
... Output Low Voltage, ports and Output Low Voltage, port 0, ALE, PSEN OL1 AT89C51CC03 168 Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
Page 169
... I would be slightly higher if a crystal oscillator used (see Figure RST = V (see Figure 79.). CC SS must be externally limited as follows: OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89C51CC03 (5) Max Unit Test Conditions = -10 μ -30 μ -60 μ ...
Page 170
... Power Fail Detect at Ambiant Temperatures AT89C51CC03 170 (1) VPFDP VPFDM 2.5V typ 2.35V typ Note: 1. Threshold Voltage for PFD Release 2. Threshold Voltage for PFD Activation Figure 78. I Test Condition, Active Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 79. I Test Condition, Idle Mode ...
Page 171
... Table 120, Table 123 and Table 126 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols: Take the x value and use this value in the formula. Example: T and 20 MHz, Standard clock. LLIV 170 ns CCIV AT89C51CC03 Tests in Active and Idle Modes CC 0.7V CC 0.2V -0 CLCH = T = 5ns ...
Page 172
... External Program Memory Characteristics AT89C51CC03 172 Table 118. Symbol Description Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T PSEN Pulse Width PLPH T PSEN to Valid Instruction In ...
Page 173
... T CLCL T T LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T TPLAZ AVLL PXIX A0-A7 INSTR IN T AVIV ADDRESS A8-A15 AT89C51CC03 Standard Clock X2 Clock X parameter ...
Page 174
... External Data Memory Characteristics AT89C51CC03 174 Table 121. Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ T ALE to Valid Data In LLDV T Address to Valid Data In AVDV T ALE ...
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... LLWL T Max LLWL T Min AVWL T Min QVWX T Min QVWH T Min WHQX T Max RLAZ T Min WHLH T Max WHLH AT89C51CC03 Standard Clock X2 Clock X parameter 2 4 ...
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... External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing – Shift Register Mode AT89C51CC03 176 T LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 T LLDV T LLWL T ...
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... Oscillator Period CLCL T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL T /T Cyclic ratio in X2 mode CHCX CLCX AT89C51CC03 Min Max 300 200 30 0 117 Standard X parameter Clock X2 Clock for -M range ...
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... External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms AT89C51CC03 178 V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL V -0.5V CC INPUT/OUTPUT 0.45V AC inputs during testing are driven at V Timing measurement are made 0 0 For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ...
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... INDICATES ADDRESS TRANSITIONS DPL OR Rt OUT FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION DPL OR Rt OUT DATA OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED AT89C51CC03 STATE3 STATE4 STATE5 ...
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... Flash/EEPROM Memory A/D Converter AT89C51CC03 180 Table 128. Timing Symbol Definitions Signals S (Hardware PSEN#,EA condition) R RST B FBUSY flag Table 129. Memory AC Timing VDD = 3V to 5.5V -40 to +85°C Symbol Parameter T Input PSEN# Valid to RST Edge SVRL T Input PSEN# Hold after RST Edge RLSX ...
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... As it can be set also to 8, 16, 32 128, the factor of will be changed to 2TPER-20ns(1) 4182O–CAN–09/08 Test conditions: capacitive load on all pins= 60 pF. Parameter Slave Mode Master Mode if the prescaler ratio equals 8. 4TPER-20ns(1) AT89C51CC03 Min Max (1) 6 (1) 3 (1) 3 (1) ...
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... SCK (SSCPOL= 1) (input) MISO (output) MOSI (input) SS (input) SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) MISO (output) MOSI (input) AT89C51CC03 182 Figure 84. SPI Slave Waveforms (SSCPHA SLCH T T CHCH SLCL T T CHCX CLCX T SLOV SLAVE MSB OUT T T CHIX IVCH ...
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... T T IVCH CHIX T T IVCL CLIX MSB IN T CLOV T CHOV Port Data MSB OUT Note: 1. handled by software using general purpose port pin. SS Note: AT89C51CC03 T CLCH T CHCL LSB IN T CLOX CLOV T CHOV CHOX BIT 6 LSB OUT Port Data T CLCH T CHCL BIT 6 LSB IN ...
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... Part Number Loader AT89C51CC03U-7CTIM AT89C51CC03U-RLTIM AT89C51CC03U-SLSIM AT89C51CC03C-7CTIM AT89C51CC03C-RLTIM AT89C51CC03C-SLSIM AT89C51CC03U-RDTIM AT89C51CC03U-S3SIM AT89C51CC03C-RDTIM AT89C51CC03C-S3SIM AT89C51CC03UA-RLTUM UART AT89C51CC03UA-SLSUM UART AT89C51CC03CA-RLTUM CAN AT89C51CC03CA-SLSUM CAN AT89C51CC03UA-RDTUM UART AT89C51CC03UA-S3SUM UART AT89C51CC03CA-S3SUM CAN AT89C51CC03CA-RDTUM CAN AT89C51CC03 184 Temperature Range Quality Grade OBSOLETE -40 to +85°C Industrial & Green -40 to +85° ...
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... Package Drawings VQFP44 4182O–CAN–09/08 AT89C51CC03 185 ...
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... DATUM "A" AND "D" DETERMINED AT DATUM PLANE H. 6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE " f " DIMENSION AT MAXIMUM MATERIAL CONDITION . DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. AT89C51CC03 186 4182O–CAN–09/08 ...
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... PLCC44 4182O–CAN–09/08 AT89C51CC03 187 ...
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... STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE. AT89C51CC03 188 4182O–CAN–09/08 ...
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... VQFP64 4182O–CAN–09/08 AT89C51CC03 189 ...
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... DATUM "A" AND "D" DETERMINED AT DATUM PLANE H. 6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE " f " DIMENSION AT MAXIMUM MATERIAL CONDITION . DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. AT89C51CC03 190 4182O–CAN–09/08 ...
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... PLCC52 4182O–CAN–09/08 AT89C51CC03 191 ...
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... Changes from 4182J 03/06 to 4182K 04/06 Changes from 4182K 04/06 to 4182L 06/07 Changes from 4182L 06/07 to 4182M 02/08 Changes from 4182M 02/087 to 4182N 03/08 AT89C51CC03 192 1. Added Icc Idle, IPD, and Rrst value in “DC Parameters for A/D Converter” on page 171. 1. Updated SFR Table. – SFR : SPSTR changed to SPSCR – ...
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... Changes from 4182N 03/08 to 4182O 09/08 4182O–CAN–09/08 1. Correction to SPDT register address Table 94 on page 139. AT89C51CC03 193 ...
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... Internal Space..................................................................................................... 23 External Space ................................................................................................... 24 Dual Data Pointer ............................................................................................... 26 Registers............................................................................................................. 27 Power Monitor ..................................................................................... 29 Description.......................................................................................................... 29 Reset .................................................................................................... 31 Introduction ......................................................................................................... 31 Reset Input ......................................................................................................... 31 Reset Output ....................................................................................................... 32 Power Management ............................................................................ 33 Introduction ......................................................................................................... 33 Idle Mode ............................................................................................................ 33 Power-Down Mode ............................................................................................. 33 Registers............................................................................................................. 36 EEPROM Data Memory ...................................................................... 37 Write Data in the Column Latches ...................................................................... 37 Programming ...................................................................................................... 37 Read Data........................................................................................................... 37 Examples ............................................................................................................ 38 AT89C51CC03 i 4182O–CAN–09/08 ...
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... Timer 1................................................................................................................ 71 Interrupt .............................................................................................................. 72 Registers............................................................................................................. 72 Timer 2 ................................................................................................. 76 Auto-Reload Mode............................................................................................. 76 Programmable Clock-Output .............................................................................. 77 Registers............................................................................................................. 78 Watchdog Timer ................................................................................. 81 Watchdog Programming ..................................................................................... 82 Watchdog Timer During Power-down Mode and Idle ......................................... 83 CAN Controller .................................................................................... 85 CAN Protocol ...................................................................................................... 85 CAN Controller Description................................................................................. 89 CAN Controller Mailbox and Registers Organization.......................................... 90 CAN Controller Management.............................................................................. 92 4182O–CAN–09/08 AT89C51CC03 ii ...
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... Clock Selection ................................................................................................. 154 ADC Standby Mode .......................................................................................... 155 IT ADC Management ........................................................................................ 155 Routines examples ........................................................................................... 155 Registers........................................................................................................... 157 Interrupt System ............................................................................... 160 Introduction ....................................................................................................... 160 Registers........................................................................................................... 162 Electrical Characteristics ................................................................. 168 Absolute Maximum Ratings .............................................................................168 ICCOP Test Conditions .................................................................................... 168 DC Parameters for Standard Voltage ...............................................................168 AT89C51CC03 iii 4182O–CAN–09/08 ...
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... Changes from 4182H 04/05 to 4182I 06/05...................................................... 192 Changes from 4182I 06/05 to 4182J 03/06 ...................................................... 192 Changes from 4182J 03/06 to 4182K 04/06 ..................................................... 192 Changes from 4182K 04/06 to 4182L 06/07..................................................... 192 Changes from 4182L 06/07 to 4182M 02/08 .................................................... 192 Changes from 4182M 02/087 to 4182N 03/08.................................................. 192 Changes from 4182N 03/08 to 4182O 09/08.................................................... 193 Table of Contents .................................................................................. i 4182O–CAN–09/08 AT89C51CC03 iv ...
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... Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. ©2008 Atmel Corporation. All rights reserved. Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. ...