AT89C51ID2 Atmel Corporation, AT89C51ID2 Datasheet
AT89C51ID2
Manufacturer Part Number
AT89C51ID2
Description
Manufacturer
Atmel Corporation
Specifications of AT89C51ID2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
2
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART
Watchdog
Yes
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Active Errata List
•
•
•
•
•
Errata History
Errata Descriptions
1. During UART Reception, Clearing REN May Generate Unexpected IT
2. Timer 2 – Baud Rate Generator
3. C51 Core
4. PCA
5. Timer0/1
Lot Number
All
During UART Reception, Clearing REN May Generate Unexpected IT
Timer 2 – Baud Rate Generator – Long Start Time
C51 Core – Bad Exit of Power-down in X2 Mode
PCA – Incorrect Behavior with CPU X2 Mode bit of HSB
Timer0/1
During UART reception, if the REN bit is cleared between start bit detection and
the end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine directly after CLR RI, and run the
Interrupt routine code only if REN is set.
When Timer 2 is used as a baud rate generator, TH2 is not loaded with RCAP2H
at the beginning, then UART is not operational before 10,000 machine cycles.
Workaround
Add the initialization of TH2 and TL2 in the initialization of Timer 2.
When exiting power-down mode by interrupt while CPU is in X2 mode, it leads to
bad execution of the first instruction run when CPU restarts.
Workaround
Set the CPU in X1 mode directly before entering power-down mode.
When starting the microcontroller in X2 mode upon reset with the X2 fuse bit of
the HSB, the PCA may not work properly when configured with Timer 0 in X1
mode as clock input.
Workaround
Set the CPU in X2 mode with software by writing CKCON register at the begin of
the application.
When the Timer0 is in X1 mode and Timer1 in X2 mode and vice versa, extra
interrupt may randomly occur for Timer0 or Timer1.
Workaround
Use the same mode for the two timers.
–
–
Incorrect behavior with CPU X2 Mode bit of HSB
Extra Interrupt
–
–
Extra Interrupt
Bad Exit of Power-down in X2 Mode
–
Long Start Time
Errata List
1, 2, 3, 4, 5
80C51 MCUs
AT89C51ID2
Errata Sheet
Rev. 4320A–8051–01/04
1
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AT89C51ID2 Summary of contents
Page 1
... When the Timer0 mode and Timer1 in X2 mode and vice versa, extra interrupt may randomly occur for Timer0 or Timer1. Workaround Use the same mode for the two timers. Errata List Long Start Time – 80C51 MCUs AT89C51ID2 Errata Sheet Rev. 4320A–8051–01/04 1 ...
Page 2
Active UART Bootloader Errata List • API Program Data Byte - Incorrect Return Value • API Program Data Page - Incorrect Return Value UART Bootloader Errata History Version Number 0.0 (1.0.0 displayed by FLIP) UART Bootloader Errata Description 1. API ...
Page 3
... FAX (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...