AT90CAN32 Automotive Atmel Corporation, AT90CAN32 Automotive Datasheet
AT90CAN32 Automotive
Specifications of AT90CAN32 Automotive
Related parts for AT90CAN32 Automotive
AT90CAN32 Automotive Summary of contents
Page 1
Features • High-performance, Low-power AVR • Advanced RISC Architecture – 133 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – MIPS ...
Page 2
Description 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 AT90CAN32, AT90CAN64 and AT90CAN128 are all hardware and software compatible with each other, the only difference is the memory size. Table 1-1. Device AT90CAN32 AT90CAN64 AT90CAN128 1.2 Part Description The AT90CAN32/64/128 ...
Page 3
RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90CAN32/64/128 AVR is supported with ...
Page 4
Block Diagram Figure 1-1. Block Diagram AT90CAN32/64/128 4 7682C–AUTO–04/08 ...
Page 5
Pin Configurations Pinout AT90CAN32/64/128 - TQFP Figure 1-2. 7682C–AUTO–04/08 AT90CAN32/64/128 5 ...
Page 6
Figure 1-3. Pinout AT90CAN32/64/128 - QFN Note: 1.7 Pin Descriptions 1.7.1 VCC Digital supply voltage. 1.7.2 GND Ground. AT90CAN32/64/128 6 The large center pad underneath the QFN package is made of metal and internally connected to GND. It should be ...
Page 7
Port A (PA7..PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A ...
Page 8
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym- metrical drive characteristics with both ...
Page 9
AVR CPU Core 3.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
Page 10
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
Page 11
Status Register The Status Register contains information about the result of the most recently executed arith- metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
Page 12
Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 3.5 General Purpose Register File The Register File is optimized for the ...
Page 13
Figure 3-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 3.5.2 Extended Z-pointer Register for ELPM/SPM – RAMPZ Bit Read/Write ...
Page 14
Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that ...
Page 15
Figure 3-6 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 3-6. 3.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset ...
Page 16
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When ...
Page 17
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini- mum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock ...
Page 18
Memories This section describes the different memories in the AT90CAN32/64/128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90CAN32/64/128 features an EEPROM Memory for data storage. All three ...
Page 19
Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory and ELPM – Extended Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in ing” on ...
Page 20
SRAM Data Access When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories ...
Page 21
Figure 4-2. 4.2.2 SRAM Data Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 4-3. 7682C–AUTO–04/08 Data Memory Map Data Memory 32 Registers 64 ...
Page 22
EEPROM Data Memory The AT90CAN32/64/128 contains EEPROM memory (see “E2 size”). It is organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase ...
Page 23
The EEPROM Data Register – EEDR Bit Read/Write Initial Value • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by ...
Page 24
Support – Read-While-Write Self-Programming” on page 320 programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting ...
Page 25
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo- bally) so that no interrupts will occur during execution of these functions. ...
Page 26
The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...
Page 27
I/O Memory The I/O space definition of the AT90CAN32/64/128 is shown in 384. All AT90CAN32/64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between ...
Page 28
Figure 4-4. 4.5.2 Using the External Memory Interface The interface consists of: • AD7:0: Multiplexed low-order address bus and data bus. • A15:8: High-order address bus (configurable number of bits). • ALE: Address latch enable. • RD: Read strobe. • ...
Page 29
Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi- tions above ...
Page 30
The access time cannot exceed the time from the ALE pulse must be asserted low until data is stable during a read sequence (see t in Tables 26-7 through Tables 26-14). The different ...
Page 31
Note: Figure 4-8. Note: Figure 4-9. Note: 7682C–AUTO–04/08 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T5 is only present if the next instruction ...
Page 32
External Memory Control Register A – XMCRA Bit Read/Write Initial Value • Bit 7 – SRE: External SRAM/XMEM Enable Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as ...
Page 33
Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter- nal memory address space, see • Bit 1..0 – SRW01, SRW00: ...
Page 34
Table 4-5. XMM2 4.5.8 Using all Locations of External Memory Smaller than 64 KB Since the external memory is mapped after the internal memory as shown in external memory is not addressed ...
Page 35
Using all 64KB Locations of External Memory Since the External Memory is mapped after the Internal Memory as shown in (64K-(“ISRAM size”+256)) bytes of External Memory is available by default (address space 0x0000 to “ISRAM end” is reserved for ...
Page 36
General Purpose I/O Registers The AT90CAN32/64/128 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. The General Purpose I/O Register 0, ...
Page 37
System Clock 5.1 Clock Systems and their Distribution Figure 5-1 need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described ...
Page 38
Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time ...
Page 39
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. C1 and C2 should always be ...
Page 40
Table 5-4. CKSEL0 Notes: 5.5 Low-frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal Oscillator must be selected by setting the ...
Page 41
When this Oscillator is selected, start-up times are determined by the SUT1..0 fuses as shown in Table 5-5 Table 5-5. SUT1.. Table 5-6. CKSEL3..0 0100 0101 0110 0111 Note: 5.6 Calibrated Internal RC Oscillator The calibrated ...
Page 42
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 5-8. Table 5-8. SUT1.. ( Note: 5.6.1 Oscillator Calibration Register – OSCCAL Bit Read/Write Initial Value • Bit 7 ...
Page 43
Figure 5-4. Table 5-10. CKSEL3..0 0000 When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 5-11. Table 5-11. SUT1.. When applying an external clock required ...
Page 44
AT90CAN32/64/128 share the Timer/Counter2 Oscillator Pins (TOSC1 and TOSC2) with PG4 and PG3. This means that both PG4 and PG3 can only be used when the Timer/Counter2 Oscil- lator is not enable. Applying an external clock source to TOSC1 can ...
Page 45
This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. Note that any ...
Page 46
Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
Page 47
Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 6.1 Idle Mode When the SM2..0 bits are written to 000, ...
Page 48
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits ...
Page 49
Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if ...
Page 50
There are three alternative ways to avoid this: • Disable OCDEN Fuse. • Disable JTAGEN Fuse. • Write one to the JTD bit in MCUCR. The TDO pin is left floating ...
Page 51
System Control and Reset 7.1 Reset 7.1.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be ...
Page 52
Figure 7-1. Table 7-1. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset Threshold Voltage (falling) V Start Voltage to ensure CC V POR internal Power-on Reset signal V Rise Rate to ensure CC V CCRR ...
Page 53
V rise. The RESET signal is activated again, without any delay, when V CC the detection level. Figure 7-2. TIME-OUT INTERNAL RESET Figure 7-3. RESET TIME-OUT INTERNAL RESET Note: 7.1.4 External Reset An External Reset is generated by a low ...
Page 54
Figure 7-4. 7.1.5 Brown-out Detection AT90CAN32/64/128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL ...
Page 55
When the BOD is enabled, and V 7-5), the Brown-out Reset is immediately activated. When V (V BOT+ expired. The BOD circuit will only detect a drop in V longer than t Figure 7-5. 7.1.6 Watchdog Reset When the Watchdog ...
Page 56
Bit 7..5 – Reserved Bits These bits are reserved for future use. • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register ...
Page 57
Voltage Reference Characteristics Table 7-4. Symbol 7.3 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at V controlling the ...
Page 58
Read/Write Initial Value • Bits 7..5 – Reserved Bits These bits are reserved bits for future use. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, ...
Page 59
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly ...
Page 60
Interrupts ...
Page 61
Table 8-1. Vector No Notes: Table 8-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be ...
Page 62
When the BOOTRST Fuse ...
Page 63
When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses ...
Page 64
Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 8.2.1 MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When ...
Page 65
Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
Page 66
I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
Page 67
Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 9-2. Note: 9.2.1 Configuring the Pin Each port pin consists of three register ...
Page 68
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
Page 69
Figure 9-3. Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region ...
Page 70
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
Page 71
Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of ...
Page 72
Figure 9-5. Note: Table 9-2 Figure 9-5 internally in the modules having the alternate function. AT90CAN32/64/128 72 (1) Alternate Port Functions PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 Pxn 0 DIEOExn DIEOVxn 1 SLEEP 0 PUOExn: ...
Page 73
Table 9-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function ...
Page 74
Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ...
Page 75
Table 9-4 in Figure 9-5 on page Table 9-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: Table 9-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 7682C–AUTO–04/08 ...
Page 76
Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-6. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • OC0A/OC1C, Bit 7 OC0A, ...
Page 77
MOSI, SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, ...
Page 78
Table 9-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 9.3.4 Alternate Functions of Port C The Port C has an alternate function as the address high byte for the External Memory Interface. The Port ...
Page 79
A14 – Port C, Bit 6 A14, External memory interface address 14. • A13 – Port C, Bit 5 A13, External memory interface address 13. • A12 – Port C, Bit 4 A12, External memory interface address 12. • ...
Page 80
Table 9-11. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 9.3.5 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 9-12. Port Pin PD7 PD6 PD5 PD4 PD3 ...
Page 81
TXCAN, CAN Transmit Data (Data output pin for the CAN). When the CAN is enabled, this pin is configured as an output regardless of the value of DDD5. XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the ...
Page 82
Table 9-13 shown in Table 9-13. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 9-14. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: AT90CAN32/64/128 82 and Table 9-14 ...
Page 83
Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 9-15. Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 The alternate pin configuration is as follows: • PCINT7/ICP3 – Port E, ...
Page 84
AIN0/XCK0 – Port E, Bit 2 AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock is ...
Page 85
Table 9-17. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 9.3.7 Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in some Port ...
Page 86
TDI, JTAG Test Data In. Serial input data to be shifted in to the Instruction Register or Data Reg- ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ...
Page 87
Table 9-19 shown in Table 9-19. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 9-20. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 7682C–AUTO–04/08 and Table 9-20 relates the ...
Page 88
Alternate Functions of Port G The alternate pin configuration is as follows: Table 9-21. Port Pin PG4 PG3 PG2 PG1 PG0 The alternate pin configuration is as follows: • TOSC1 – Port G, Bit 4 TOSC2, Timer/Counter2 Oscillator pin ...
Page 89
Table 9-21 shown in Table 9-22. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 9-23. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 9.4 Register Description for I/O-Ports 9.4.1 ...
Page 90
Port A Data Direction Register – DDRA Bit Read/Write Initial Value 9.4.3 Port A Input Pins Address – PINA Bit Read/Write Initial Value 9.4.4 Port B Data Register – PORTB Bit Read/Write Initial Value 9.4.5 Port B Data Direction ...
Page 91
Port D Data Register – PORTD Bit Read/Write Initial Value 9.4.11 Port D Data Direction Register – DDRD Bit Read/Write Initial Value 9.4.12 Port D Input Pins Address – PIND Bit Read/Write Initial Value 9.4.13 Port E Data Register ...
Page 92
Port F Input Pins Address – PINF Bit Read/Write Initial Value 9.4.19 Port G Data Register – PORTG Bit Read/Write Initial Value 9.4.20 Port G Data Direction Register – DDRG Bit Read/Write Initial Value 9.4.21 Port G Input Pins ...
Page 93
External Interrupts The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of gen- erating a software interrupt. ...
Page 94
Table 10-1. ISCn1 Note: Table 10-2. Symbol t INT 10.0.2 Synchronous External Interrupt Control Register B – EICRB Bit Read/Write Initial Value • Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: Synchronous External Interrupt 7 - ...
Page 95
External Interrupt Mask Register – EIMSK Bit Read/Write Initial Value • Bits 7..0 – INT7 – INT0: External Interrupt Request Enable When an INT7 – INT0 bit is written to one and the I-bit in the ...
Page 96
Timer/Counter3/1/0 Prescalers Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter3, Timer/Counter1 and Timer/Counter0. 11.1 Overview Most bit references in this section are written ...
Page 97
Figure 11-1. T3/T1/T0 Pin Sampling The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T3/T1/T0 pin to the counter is updated. Enabling and disabling of ...
Page 98
Timer/Counter0/1/3 Prescalers Register Description 11.2.1 General Timer/Counter Control Register – GTCCR Bit Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value ...
Page 99
Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 12.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator ...
Page 100
Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter- rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the ...
Page 101
Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source ...
Page 102
Figure 12-3 Figure 12-3. Output Compare Unit, Block Diagram The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ...
Page 103
Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...
Page 104
Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0A1 tells the Waveform Generator that no action on the OC0A Register ...
Page 105
Figure 12-5. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the ...
Page 106
PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 12-6. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If ...
Page 107
Phase Correct PWM Mode The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM ...
Page 108
The PWM frequency for the output when using phase correct PWM can be calcu- lated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register ...
Page 109
Figure 12-10 Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f Figure 12-11 Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- 12.9 8-bit Timer/Counter Register Description 12.9.1 Timer/Counter0 Control Register A – TCCR0A ...
Page 110
Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by ...
Page 111
Note: Table 12-4 rect PWM mode. Table 12-4. COM0A1 Note: • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 12-5. CS02 0 ...
Page 112
Output Compare Register A – OCR0A Bit Read/Write Initial Value The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, ...
Page 113
Timer/Counter (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: 13.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Three independent ...
Page 114
Figure 13-1. 16-bit Timer/Counter Block Diagram Note: 13.2.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in ...
Page 115
The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCRnx) are ...
Page 116
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. The following bits are added to the 16-bit Timer/Counter Control Registers: • COMnC1:0 are added to TCCRnA. • FOCnA, FOCnB and FOCnC are added to TCCRnC. ...
Page 117
Code Examples The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnx and ICRn Registers. Note that when ...
Page 118
The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: ; Save global interrupt ...
Page 119
The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...
Page 120
Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 Figure 13-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
Page 121
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 13.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
Page 122
Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading ...
Page 123
Using the Input Capture unit in any mode of operation when the TOP value (resolution) ...
Page 124
Figure 13-4. Output Compare Unit, Block Diagram The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is ...
Page 125
COMnx1:0 bits settings define whether the OCnx pin is set, cleared or toggled). 13.7.2 Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the ...
Page 126
Figure 13-5. Compare Match Output Unit, Schematic 13.8.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction ...
Page 127
Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out- put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared ...
Page 128
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the inter- rupt is enabled, the ...
Page 129
PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small ...
Page 130
In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to ...
Page 131
The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The ...
Page 132
The PWM waveform is generated by setting (or clearing) the OCnx Regis- ter at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and ...
Page 133
Figure 13-9. Phase and Frequency Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ...
Page 134
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set ...
Page 135
Figure 13-12. Timer/Counter Timing Diagram, no Prescaling Figure 13-13 Figure 13-13. Timer/Counter Timing Diagram, with Prescaler (f 13.11 16-bit Timer/Counter Register Description 13.11.1 Timer/Counter1 Control Register A – TCCR1A Bit Read/Write Initial Value 13.11.2 Timer/Counter3 Control Register A – TCCR3A ...
Page 136
Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B • Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0 and COMnC1:0 control the ...
Page 137
Table 13-3 correct or the phase and frequency correct, PWM mode. Table 13-3. COMnA1/COMnB1/ COMnC1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence ...
Page 138
Table 13-4. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...
Page 139
This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit ...
Page 140
Timer/Counter3 Control Register C – TCCR3C Bit Read/Write Initial Value • Bit 7 – FOCnA: Force Output Compare for Channel A • Bit 6 – FOCnB: Force Output Compare for Channel B • Bit 5 – FOCnC: Force Output ...
Page 141
Output Compare Register A – OCR1AH and OCR1AL Bit Read/Write Initial Value 13.11.10 Output Compare Register B – OCR1BH and OCR1BL Bit Read/Write Initial Value 13.11.11 Output Compare Register C – OCR1CH and OCR1CL Bit Read/Write Initial Value 13.11.12 ...
Page 142
Input Capture Register – ICR1H and ICR1L Bit Read/Write Initial Value 13.11.16 Input Capture Register – ICR3H and ICR3L Bit Read/Write Initial Value The Input Capture is updated with the counter (TCNTn) value each time an event occurs on ...
Page 143
Bit 2 – OCIEnB: Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The ...
Page 144
Bit 2 – OCFnB: Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe will ...
Page 145
Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 14.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct ...
Page 146
Figure 14-1. 8-bit Timer/Counter2 Block Diagram The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter- rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with ...
Page 147
Definitions The following definitions are used extensively throughout the section: BOTTOM MAX TOP 14.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source is selected by the ...
Page 148
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22 the timer is stopped. However, ...
Page 149
Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2A Register access may seem complex, but this is not case. When the double ...
Page 150
Figure 14-5. Compare Match Output Unit, Schematic 14.6.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction ...
Page 151
For detailed timing information refer to 14.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply ...
Page 152
For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will ...
Page 153
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation ...
Page 154
Figure 14-8. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In ...
Page 155
Figure 14-9. Timer/Counter Timing Diagram, no Prescaling Figure 14-10 Figure 14-10. Timer/Counter Timing Diagram, with Prescaler (f Figure 14-11 Figure 14-11. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f 7682C–AUTO–04/08 shows the same timing data, but with the prescaler ...
Page 156
Figure 14-12 Figure 14-12. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- 14.9 8-bit Timer/Counter Register Description 14.9.1 Timer/Counter2 Control Register A– TCCR2A Bit Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The ...
Page 157
Pulse Width Modulation (PWM) modes. See on page Table 14-1. Mode Note: • Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one ...
Page 158
Table 14-4 rect PWM mode. Table 14-4. COM2A1 Note: • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 14-5. Table 14-5. CS22 ...
Page 159
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2A pin. 14.10 ...
Page 160
Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching ...
Page 161
Description of wake up from Power-save mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always ...
Page 162
Bit 7..2 – Reserved Bits These bits are reserved for future use. • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data ...
Page 163
Figure 14-14. Timer/Counter2 Crystal Oscillator Connections A external clock can also be used using TOSC1 as input. Setting AS2 and EXCLK enables this configuration. Figure 14-15. Timer/Counter2 External Clock Connections For Timer/Counter2, the possible prescaled selections are: clk clk /128, ...
Page 164
Output Compare Modulator - OCM 15.1 Overview Many register and bit references in this section are written in general form. • A lower case “n” replaces the Timer/Counter number, in this case 0 and 1. However, when using the ...
Page 165
Figure 15-2. Output Compare Modulator, Schematic 15.2.1 Timing Example Figure 15-3 ate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 15-3. Output Compare Modulator, Timing Diagram In this ...
Page 166
Resolution of the PWM Signal The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is equal to the number of system clock cycles of one period of the carrier (OC0A). In this example ...
Page 167
Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90CAN32/64/128 and peripheral devices or between several AVR devices. The AT90CAN32/64/128 SPI includes the following features: 16.1 Features • Full-duplex, Three-wire Synchronous ...
Page 168
The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
Page 169
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 16-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...
Page 170
DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin ...
Page 171
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 16.2 SS Pin ...
Page 172
Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the ...
Page 173
SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas- ter mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. ...
Page 174
SPI Status Register – SPSR Bit Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and ...
Page 175
This is clearly seen by summarizing Table 16-2 Table 16-5. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 16-3. SPI Transfer Format with CPHA = 0 Figure 16-4. SPI Transfer ...
Page 176
USART (USART0 and USART1) The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: 17.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous ...
Page 177
Figure 17-1. USARTn Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USARTn (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation ...
Page 178
Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in ...
Page 179
UMSELn, U2Xn and DDR_XCKn bits. Table 17-1 ing the UBRRn value for each mode of operation using an internally ...
Page 180
Note that to add some margin to avoid possible loss of data due to frequency variations. 17.4.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or ...
Page 181
Figure 17-4. Frame Formats St ( IDLE The frame format used by the USARTn is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing ...
Page 182
Note that the TXCn flag must be cleared before each transmission (before UDRn is written used for this purpose. The following simple USART0 initialization code examples ...
Page 183
XCKn pin will be overridden and used as transmission clock. 17.7.1 Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the data ...
Page 184
Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8n bit in UCS- RnB before the low byte of the character is written to UDRn. The ...
Page 185
The Data Register Empty (UDREn) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has ...
Page 186
The following code example shows a simple USART0 receive function based on polling of the Receive Complete (RXC0) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR0 will be ...
Page 187
The following code example shows a simple USART0 receive function that handles both nine bit characters and the status bits. Assembly Code Example USART0_Receive: USART0_ReceiveNoError: C Code Example unsigned int USART0_Receive(void Note: The receive function example reads all ...
Page 188
Receive Complete Flag and Interrupt The USARTn Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data ...
Page 189
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until ...
Page 190
Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., ...
Page 191
Figure 17-7 of the next frame. Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is ...
Page 192
Table 17-2. # (Data + Parity Bit) Table 17-3. # (Data + Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. ...
Page 193
MPCM Protocol If the Receiver is set up to receive frames that contain data bits, then the first stop bit indi- cates if the frame contains data or address information. If the Receiver is set up ...
Page 194
USART Register Description 17.11.1 USART0 I/O Data Register – UDR0 Bit Read/Write Initial Value 17.11.2 USART1 I/O Data Register – UDR1 Bit Read/Write Initial Value • Bit 7:0 – RxBn7:0: Receive Data Buffer (read access) • Bit 7:0 – ...
Page 195
Bit 6 – TXCn: USARTn Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn). The ...
Page 196
USART1 Control and Status Register B – UCSR1B Bit Read/Write Initial Value • Bit 7 – RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn flag. A USARTn Receive Complete inter- rupt will ...
Page 197
USART1 Control and Status Register C – UCSR1C Bit Read/Write Initial Value • Bit 7 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, these bit must be written to zero when UCSRnC ...
Page 198
Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe frame the Receiver and Transmitter use. Table 17-7. UCSZn2 • Bit 0 – ...
Page 199
Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH is written. • Bit 11:0 – UBRRn11:0: USARTn Baud Rate Register This is ...
Page 200
Table 17-10. Examples of UBRRn Settings for Commonly Frequencies (Continued 3.6864 MHz clk io Baud Rate U2Xn = 0 U2Xn = 1 (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 ...