AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet
AT90PWM1
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AT90PWM1 Summary of contents
Page 1
... Power On Reset and Programmable Brown Out Detection – Flag Array in Bit-programmable I/O Space (4 bytes) – In-System Programmable via SPI Port – Internal Calibrated RC Oscillator ( 8 MHz) – On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz) 8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT90PWM1 4378C–AVR–09/08 ...
Page 2
... Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max val- ues will be available after the device is characterized. 3. Pin Configurations Figure 3-1. AT90PWM1 2 Revision First revision of parts SOIC 24-pin Package 4378C–AVR–09/08 ...
Page 3
... Figure 3-2. (PSCIN2/OC1A/MISO_A) PD2 4378C–AVR–09/08 QFN 32 -pin Package AT90PWM1 QFN 32 1 (OC0A/SS/MOSI_A) PD3 VCC 4 GND (MISO/PSCOUT20) PB0 8 AT90PWM1 24 PB4 (AMP0+) 23 PB3 (AMP0 AREF AGND 20 AVCC ...
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... AT90PWM1 4 Mnemonic Type GND Power Ground: 0V reference AGND Power Analog Ground: 0V reference for analog part VCC power Power Supply: Analog Power Supply: This is the power supply voltage for analog part AVCC Power For a normal use this pin must be connected. ...
Page 5
... Overview The AT90PWM1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM1 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. ...
Page 6
... CISC microcontrollers. The AT90PWM1 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, 2 Power Stage Controllers, two flexible ...
Page 7
... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90PWM1 as listed on 68. 4378C–AVR–09/08 ...
Page 8
... Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C compiler documen- tation for more details. AT90PWM1 8 Table 9-1 on page , even if the ADC is not used. If the ADC is used, it should be connected ...
Page 9
... The program memory is In-System Reprogrammable Flash memory. 4378C–AVR–09/08 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines AT90PWM1 Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
Page 10
... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90PWM1 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
Page 11
... Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 4378C–AVR–09/ R/W R/W R/W R ⊕ V AT90PWM1 R/W R/W R/W R SREG 11 ...
Page 12
... The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in AT90PWM1 12 shows the structure of the 32 general purpose working registers in the CPU. ...
Page 13
... SP6 SP5 SP4 SP3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R directly generated from the selected clock source for the CPU AT90PWM1 R26 (0x1A R28 (0x1C R30 (0x1E SP10 SP9 SP8 SPH SP2 SP1 SP0 SPL R/W R/W R/W R/W ...
Page 14
... Event. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to mation. The Reset Vector can also be moved to the start of the Boot Flash section by AT90PWM1 14 shows the parallel instruction fetches and instruction executions enabled by the Har- ...
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... EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ AT90PWM1 15 ...
Page 16
... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. AT90PWM1 16 Assembly Code Example sei ...
Page 17
... Memories This section describes the different memories in the AT90PWM1. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90PWM1 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
Page 18
... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 512 bytes of internal data SRAM in the AT90PWM1 are all accessible through all these addressing modes. The Register File is described in 12. ...
Page 19
... EEPROM Data Memory The AT90PWM1 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 20
... Read/Write Initial Value • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM1 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...
Page 21
... The user should poll the EEWE bit before starting the read operation write operation is in progress neither possible to read the EEPROM, nor to change the EEAR Register. 4378C–AVR–09/08 AT90PWM1 “Boot Loader for details about Boot 21 ...
Page 22
... The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. AT90PWM1 22 Number of Calibrated RC Oscillator Cycles ...
Page 23
... EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); AT90PWM1 23 ...
Page 24
... Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V be used reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. AT90PWM1 24 r16,EEDR ; ...
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... I/O Memory The I/O space definition of the AT90PWM1 is shown in All AT90PWM1 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions ...
Page 26
... Read/Write Initial Value AT90PWM1 26 GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 R/W R/W R/W R GPIOR3 R/W R/W R/W R 4378C–AVR–09/08 ...
Page 27
... General I/O ADC Modules CLK PLL PLL clk AVR Clock I/O Control Unit PLL Input Clock Multiplexer Multiplexer External Clock AT90PWM1 “Power Management and CPU Core RAM clk ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source Clock Watchdog Clock Watchdog Oscillator ...
Page 28
... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in AT90PWM1 28 Device Clocking Options Select AT90PWM1 System CKSEL3..0 (1) Clock ...
Page 29
... Typ Time-out ( Table 7-3. For ceramic resonators, the capacitor values given by Crystal Oscillator Connections Crystal Oscillator Operating Modes (1) Frequency Range (MHz) (2) 0.4 - 0.9 AT90PWM1 “Watchdog Oscillator = 3.0V) Number of Cycles CC 4 Figure 7-2. Either a quartz crystal XTAL2 C1 XTAL1 GND Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
Page 30
... This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 7-5. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically cal- AT90PWM1 30 Crystal Oscillator Operating Modes (1) Frequency Range (MHz) 0 ...
Page 31
... The device is shipped with this option selected. Oscillator Calibration Register – OSCCAL CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value AT90PWM1 “Oscillator Calibration Register – OSCCAL” on Table 23-1 on page 223. (1)(2) CKSEL3..0 0010 Additional Delay from Reset (V = 5.0V) CC (1) 14CK 14CK + 4 ...
Page 32
... Internal PLL for PSC The internal PLL in AT90PWM1 generates a clock frequency that is 64x multiplied from nomi- nally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is divided down to 1 MHz. See the The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register will adjust the fast peripheral clock at the same time ...
Page 33
... Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM1 and always read as zero. • Bit 2 – PLLF: PLL Factor The PLLF bit is used to select the division factor of the PLL. If PLLF is set, the PLL output is 64Mhz. ...
Page 34
... MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior required to ensure that the MCU is kept in Reset during such changes in the clock frequency. AT90PWM1 34 for PSC. After the PLL is enabled, it takes about 100 ms for the PLL to lock. ...
Page 35
... System Clock Prescaler The AT90PWM1 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 36
... The device is shipped with the CKDIV8 Fuse programmed. Table 7-11. CLKPS3 AT90PWM1 36 Clock Prescaler Select CLKPS2 CLKPS1 ...
Page 37
... To avoid the MCU entering the sleep mode unless it is the programmer’s purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 4378C–AVR–09/08 presents the different clock systems in the AT90PWM1, and their distribu – ...
Page 38
... Reset Time-out period, as described in 8.4 Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down AT90PWM1 38 , while allowing the other clocks to run. “Clock Sources” on page , clk ...
Page 39
... Bit 6 - PRPSC1: Power Reduction PSC1 4378C–AVR–09/08 Active Clock Domains (1) 1. Only recommended with external crystal or resonator selected as clock source. 2. Only level interrupt PRPSC2 PRPSC1 PRPSC0 R/W R/W R AT90PWM1 Oscillator s Wake-up Sources ( ( ( PRTIM1 ...
Page 40
... If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig- AT90PWM1 40 “Analog Comparator” on page 176 for details on how to configure the Analog 4378C– ...
Page 41
... Digital CC page 180 and page 199 for details. AT90PWM1 “Brown-out Detection” on page 45 ) are stopped, the input buffers of the device will for details on which pins are enabled. If the for details “Internal Volt- ...
Page 42
... SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in 9.0.2 Reset Sources The AT90PWM1 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
Page 43
... The Power-on Reset will not work unless the supply voltage has been below V Table 9-1. The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level. CC AT90PWM1 DATA BUS MCU Status Register (MCUSR) Circuit Delay Counters Clock ...
Page 44
... An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V the Time-out period – t Figure 9-4. AT90PWM1 44 MCU Start-up, RESET Tied POT V ...
Page 45
... Brown-out Detection AT90PWM1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
Page 46
... Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag AT90PWM1 46 Brown-out Reset During Operation V CC ...
Page 47
... Internal Voltage Reference AT90PWM1 features an internal bandgap reference. This reference is used for Brown-out Detection. It can also be used as a voltage reference for the DAC and/or the ADC, and can be used as analog input for the analog comparators. In order to use the internal Vref necessary to configure it thanks to the REFS1 and REFS0 bits in the ADMUX register and to set an analog feature which requires it ...
Page 48
... Watchdog Timer AT90PWM1 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 9-7 ...
Page 49
... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. The example code assumes that the part specific header file is included. AT90PWM1 49 ...
Page 50
... This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. AT90PWM1 50 (1) r16, (1<<WDCE) | (1<<WDE) Got four cycles to set the new values from here - r16, (1< ...
Page 51
... Interrupt Mode 1 0 System Reset Mode Interrupt and System Reset 1 1 Mode x x System Reset Mode 1. For the WDTON Fuse “1” means unprogrammed while “0” means programmed. 52. AT90PWM1 Action on Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset 51 ...
Page 52
... Table 9-6. WDP3 AT90PWM1 52 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles (4096) cycles (8192) cycles 16K (16384) cycles 32K (32768) cycles ...
Page 53
... Interrupts This section describes the specifics of the interrupt handling as performed in AT90PWM1. For a general explanation of the AVR interrupt handling, refer to page 14. 10.1 Interrupt Vectors in AT90PWM1 Table 5. Reset and Interrupt Vectors Vector No ...
Page 54
... IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 6. Reset and Interrupt Vectors Placement in AT90PWM1 BOOTRST 1 1 ...
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... When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM1 is: Address Labels Code .org 0x001 0x001 0x002 ... ...
Page 56
... When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM1 is: Address Labels Code ...
Page 57
... MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); AT90PWM1 “Boot Loader Support – for details on Boot Lock bits. 57 ...
Page 58
... Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. AT90PWM1 58 “Electrical Characteristics(1)” on page 238 Pxn ...
Page 59
... SLEEP: SLEEP CONTROL clk : I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 72, the DDxn bits are accessed at the DDRx I/O address, the AT90PWM1 Figure 11 DDxn Q CLR ...
Page 60
... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. gram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t AT90PWM1 60 summarizes the control signals for the pin value. PUD ...
Page 61
... The out instruction sets the “SYNC LATCH” signal at the positive edge of through the synchronizer is 1 system clock period. pd SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 AT90PWM1 XXX in r17, PINx 0x00 t pd, max t pd, min , a single signal transition on the pin will be delayed 0xFF ...
Page 62
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. AT90PWM1 62 (1) r16, (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17, (1< ...
Page 63
... WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port indexes from AT90PWM1 Figure 11-2 can be overridden by ...
Page 64
... AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. AT90PWM1 64 Full Name Description If this signal is set, the pull-up enable is controlled by the PUOV Pull-up Override signal ...
Page 65
... ADC6 (Analog Input Channel 6) INT2 AMP0+ (Analog Differential Amplifier 0 Input Channel ) AMP0- (Analog Differential Amplifier 0 Input Channel ) ADC5 (Analog Input Channel5 ) INT1 MOSI (SPI Master Out Slave In) PSCOUT21 output MISO (SPI Master In Slave Out) PSCOUT20 output AT90PWM1 – – IVSEL IVCE R ...
Page 66
... DDB0. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be controlled by the PORTB0 and PUD bits. PSCOUT20: Output 0 of PSC 2. AT90PWM1 ...
Page 67
... SCKin • SPIPS • ICP1B ireset ADC4 ADC7 PB3/AMP0- PB2/ADC5/INT1 AMP0ND ADC5D + In1en 0 In1en INT1 AMP0- ADC5 AT90PWM1 PB5/ADC6/ INT2 PB4/AMP0 ADC6D + In2en AMP0ND In2en 0 INT2 ADC6 AMP0+ PB1/MOSI/ PB0/MISO/ PSCOUT21 PSCOUT20 – ...
Page 68
... ACMP2, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Ana- log Comparator. • ADC1/ICP1/SCK_A – Bit 4 ADC1, Analog to Digital Converter, input channel 1. AT90PWM1 68 Alternate Function ACMP0 (Analog Comparator 0 Positive Input ) ADC3 (Analog Input Channel 3 ) ...
Page 69
... DDD0 slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD0. When the pin is forced input, the pull-up can still be controlled by the PORTD0 bit. 4378C–AVR–09/08 AT90PWM1 69 ...
Page 70
... Table 13 Figure 11-5 on page Table 13. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO AT90PWM1 70 and Table 14 relates the alternate functions of Port D to the overriding signals shown in 63. PD7/ PD6/ADC3/ ACMP0 ACMPM/INT0 ...
Page 71
... SS MOSI_Ain Alternate Function XTAL2: XTAL Output ADC0 (Analog Input Channel 0) XTAL1: XTAL Input OC0B (Timer 0 Output Compare B) RESET# (Reset Input) OCD (On Chip Debug I/O) AT90PWM1 PD1/PSCIN0/ PD0/PSCOUT00/ CLKO SS_A SPE • 0 MSTR • SPIPS 0 PD0 • PUD PSCen00 + SPE • 0 MSTR • ...
Page 72
... DIEOV DI AIO 11.4 Register Description for I/O-Ports 11.4.1 Port B Data Register – PORTB Bit Read/Write Initial Value 11.4.2 Port B Data Direction Register – DDRB Bit Read/Write AT90PWM1 72 relates the alternate functions of Port E to the overriding signals shown in 63. PE2/ADC0/ XTAL2 ADC0D 0 ...
Page 73
... – – – – – – – – AT90PWM1 PINB3 PINB2 PINB1 PINB0 R/W R/W R/W R/W N/A N/A N/A N PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R ...
Page 74
... If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Table 17. Interrupt Sense Control ISCn1 AT90PWM1 74 27. The I/O clock is halted in all sleep modes except Idle “Electrical Characteristics(1)” on page 27. If the level is sampled twice by the Watchdog Oscillator clock but disappears before ...
Page 75
... When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed R/W R/W R R/W R/W R AT90PWM1 INT3 INT2 INT1 R/W R/W R/W R INTF3 INTF2 INTF1 R/W ...
Page 76
... Tn/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. AT90PWM1 76 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ) ...
Page 77
... Since the edge detector uses ExtClk clk_I/O clk I/O T0 Synchronization T1 Synchronization clk 1. The synchronization logic on the input pins ( TSM ICPSEL1 – R/W R AT90PWM1 (1) Clear T1 Tn/T0) is shown in Figure 13- – – – – ...
Page 78
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. AT90PWM1 78 Table . ...
Page 79
... Control Logic direction TOP BOTTOM Timer/Counter TCNTn = = 0 = OCRnx Fixed TOP Values = OCRnx TCCRnA TCCRnB AT90PWM1 Figure 14-1. For the actual 7. CPU accessible I/O Registers, 89. must be written to zero to enable TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCnA (Int.Req.) Waveform OCnA Generation OCnB (Int ...
Page 80
... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 14-2 shows a block diagram of the counter and its surroundings. Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): AT90PWM1 80 Table 19 are also used extensively throughout the document. The counter reaches the BOTTOM when it becomes 0x00. ...
Page 81
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 84. (“Modes of Operation” on page shows a block diagram of the Output Compare unit. AT90PWM1 in the following. T0 “Modes of 84). 81 ...
Page 82
... TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. AT90PWM1 82 DATA BUS OCRnx = ...
Page 83
... OC0x Register performed on the next compare match. For compare output actions in the 4378C–AVR–09/08 COMnx1 Waveform COMnx0 D Generator FOCn D PORT D clk I/O See “8-bit Timer/Counter Register Description” on page 89. AT90PWM1 Figure 14-4 shows a simplified Q 1 OCnx OCnx Pin DDR 83 ...
Page 84
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. AT90PWM1 84 Table 20 on page 90. For fast PWM mode, refer to Table 22 on page 90 ...
Page 85
... PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and 4378C–AVR–09/ clk_I ------------------------------------------------- - ⋅ ⋅ ( OCnx OCRnx Figure 14-6. The TCNT0 value is in the timing diagram shown as a his- AT90PWM1 OCnx Interrupt Flag Set (COMnx1 OC0 ) 85 ...
Page 86
... OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. AT90PWM1 ...
Page 87
... TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare 4378C–AVR–09/08 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 Table 25 on page AT90PWM1 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...
Page 88
... MAX value in all modes other than phase correct PWM mode. Figure 14-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk I/O TCNTn TOVn Figure 14-9 AT90PWM1 88 f OCnxPCPWM Figure 14-7 Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) MAX - 1 shows the same timing data, but with the prescaler enabled ...
Page 89
... OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - COM0A1 COM0A0 COM0B1 R/W R/W R AT90PWM1 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP COM0B0 – – WGM01 R ...
Page 90
... PWM mode. Table 22. Compare Output Mode, Phase Correct PWM Mode COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode AT90PWM1 90 Table 20 shows the COM0A1:0 bit functionality when the WGM02:0 bits COM0A0 Description 0 Normal port operation, OC0A disconnected. 1 Toggle OC0A on Compare Match ...
Page 91
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90PWM1 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode 4378C–AVR–09/08 Table 23 shows the COM0B1:0 bit functionality when the WGM02:0 bits ...
Page 92
... TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a AT90PWM1 92 Table 26. Modes of operation supported by the Timer/Counter ...
Page 93
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the AT90PWM1 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 94
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM1 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 95
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 4378C–AVR–09/08 AT90PWM1 Table 92. 26, “Waveform ...
Page 96
... I/O pins, refer to including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the The PRTIM1 bit in Timer/Counter1 module. AT90PWM1 96 “Pin Descriptions” on page “16-bit Timer/Counter Register Description” on page “Power Reduction Register” on page 39 Figure 15-1 ...
Page 97
... Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Table on page 4 1. Refer to for Timer/Counter1 pin placement and description. The compare match event will also set the Compare Match Flag (OCFnx) AT90PWM1 (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = ...
Page 98
... The same principle can be used directly for accessing the OCRnx and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. AT90PWM1 98 The counter reaches the BOTTOM when it becomes 0x0000. The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). ...
Page 99
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM1 99 ...
Page 100
... SREG = sreg; return i; } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. AT90PWM1 100 (1) (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” ...
Page 101
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. “Timer/Counter0 and Timer/Counter1 Prescalers” on page AT90PWM1 76. 101 ...
Page 102
... Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. AT90PWM1 102 shows a block diagram of the counter and its surroundings. DATA BUS ...
Page 103
... ICRnL. 4378C–AVR–09/08 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ICPSEL1 ICPnA ICPnB AT90PWM1 Figure 15-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) ...
Page 104
... Compare Flag (OCFnx) at the next “timer clock cycle”. If enabled (OCIEnx = 1), the Output Com- pare Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writ- AT90PWM1 104 98. 76). The edge detector is also identical. However, when the noise canceler is “ ...
Page 105
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM AT90PWM1 96.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 106
... PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin system reset occur, the OCnx Register is reset to “0”. AT90PWM1 106 98. “Accessing 16-bit Registers” ...
Page 107
... The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out- 4378C–AVR–09/08 Waveform Generator I/O See “16-bit Timer/Counter Register Description” on page 116. Table 29 on page AT90PWM1 OCnx ...
Page 108
... Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the AT90PWM1 108 106.) “Timer/Counter Timing Diagrams” on page Figure 1 2 ...
Page 109
... OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. 4378C–AVR–09/ when OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - ⋅ OCnA FPWM AT90PWM1 f clk_I/O ⋅ OCRnA ( ) log 1 TOP + ---------------------------------- - log Figure 15-7 ...
Page 110
... The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). AT90PWM1 110 1 2 ...
Page 111
... TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Inter- rupt Flag will be set when a compare match occurs. 4378C–AVR–09/08 f clk_I ---------------------------------- - ⋅ ( OCnxPWM TOP = f /2 when OCRnA is set to zero (0x0000). This feature clk_I log 1 TOP + R = ---------------------------------- - PCPWM log AT90PWM1 ) Figure 15-8. The figure 111 ...
Page 112
... OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Regis- ter at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when AT90PWM1 112 1 2 ...
Page 113
... PWM outputs. The small horizontal line marks on the TCNTn slopes repre- sent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. 4378C–AVR–09/08 f OCnxPCPWM 15-9 PFCPWM Figure 15-9. The figure shows phase and frequency correct AT90PWM1 f clk_I/O = --------------------------- - ⋅ ⋅ TOP ( ) log 1 ...
Page 114
... OCnx Register at compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). AT90PWM1 114 1 2 ...
Page 115
... I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the count sequence close to TOP in various modes. When using phase and AT90PWM1 ) is therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx Value OCRnx OCRnx + 1 OCRnx Value OCRnx + 2 /8) clk_I/O ...
Page 116
... If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the AT90PWM1 116 clk ...
Page 117
... COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase cor- COMnA0/COMnB0 AT90PWM1 shows the COMnx1:0 bit functionality when the Description Normal port operation, OCnA/OCnB disconnected. Toggle OCnA/OCnB on Compare Match. Clear OCnA/OCnB on Compare Match (Set output to low level). Set OCnA/OCnB on Compare Match (Set output to high level). (1) Description Normal port operation, OCnA/OCnB disconnected ...
Page 118
... ICPn pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICESn: Input Capture Edge Select AT90PWM1 118 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. ...
Page 119
... I External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge FOC1A FOC1B – R/W R AT90PWM1 – – – – Figure 0 – TCCR1C R 0 ...
Page 120
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. AT90PWM1 120 7 6 ...
Page 121
... When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Reset and Interrupt Vectors Placement in AT90PWM1(1)” on page 54) is executed when the OCF1A Flag, located in TIFR1, is set. ...
Page 122
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM1, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3 used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value ...
Page 123
... Zero crossing retriggering • Demagnetization retriggering • Fault input The PSC can be chained and synchronized to provide a configuration to drive three half bridges. Thanks to this feature it is possible to generate a three phase waveforms for applications such as Asynchronous or BLDC motor drive. 4378C–AVR–09/08 AT90PWM1 123 ...
Page 124
... The PSC is seen as two symetrical entities. One part named part A which generates the output PSCOUTn0 and the second one named part B which generates the PSCOUTn1 output. Each part has its own PSC Input Module to manage selected input. AT90PWM1 124 PSC Counter ...
Page 125
... PSC Input = Module A OCRnRA Waveform = Generator A OCRnSA Part B PICRn PCNFn PFRCnB PCTLn PFRCnA (See “Output Matrix” on page AT90PWM1 PSCOUTn3 POS23 PSCOUTn1 ( From Analog Comparator n Ouput ) PSCn Input B Output PISELnB Matrix PSCn Input A PSCINn PISELnA PSCOUTn2 POS22 PSCOUTn0 POM2(PSC2 only) PSOCn 151 ...
Page 126
... The polarity “active high” or “active low” of the PSC outputs is programmable. All the timing dia- grams in the following examples are given in the “active high” polarity. 16.4 Signal Description Figure 16-3. PSC External Block View Note: AT90PWM1 126 CLK PLL CLK I/O SYnIn ...
Page 127
... Input 1 used for Retrigger or Fault functions Description PSC n Output 0 (from part A of PSC) PSC n Output 1 (from part B of PSC) PSC n Output 2 (from part A or part B of PSC) PSC n Output 3 (from part A or part B of PSC) AT90PWM1 Type Width Register 12 bits Register ...
Page 128
... B in the following figure. The complete waveform is ended with the end of sub-cycle B. It means at the end of waveform B. Figure 16-4. Cycle Presentation & 4 Ramp Mode 4 Ramp Mode 2 Ramp Mode 1 Ramp Mode AT90PWM1 128 Description (1) Synchronization Output PSC n Input Capture Register Counter value at retriggering event ...
Page 129
... Figure 16-6. PSCn0 & PSCn1 Basic Waveforms in Four Ramp mode PSC Counter PSCOUTn0 PSCOUTn1 The input clock of PSC is given by CLKPSC. 4378C–AVR–09/08 Four Ramp mode Two Ramp mode One Ramp mode Center Aligned mode OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle AT90PWM1 PSC Cycle OCRnRB OCRnSB 0 On-Time 1 Dead-Time 1 UPDATE 129 ...
Page 130
... On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time 1 = (OCRnSBH 1/Fclkpsc Note: 16.5.2.3 One Ramp Mode In One Ramp mode, PSCOUTn0 and PSCOUTn1 outputs can overlap each other. AT90PWM1 130 Minimal value for Dead-Time 0 and Dead-Time 1/Fclkpsc OCRnRA OCRnSA OCRnSB 0 0 ...
Page 131
... Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) * 1/Fclkpsc Note: 16.5.2.4 Center Aligned Mode In center aligned mode, the center of PSCn00 and PSCn01 signals are centered. 4378C–AVR–09/08 OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 = 1/Fclkpsc AT90PWM1 OCRnRB OCRnSB On-Time 1 Dead-Time 1 131 ...
Page 132
... OCRnRAH/L is not used to control PSC Output waveform timing. Nevertheless, it can be useful to adjust ADC synchronization ( Figure 16-10. Run and Stop Mechanism in Centered Mode Note: AT90PWM1 132 Minimal value for PSC Cycle = 2 * 1/Fclkpsc See “Analog Synchronization” on page 152. See “PSC 0 Control Register – PCTL0” on page ) ...
Page 133
... Cycles are grouped into frames of 16 cycles. Cycles are modulated by a sequence given by the 4378C–AVR–09/08 Regulation Loop Writting in Calculation PSC Registers Cycle Cycle Cycle Cycle With Set i With Set i With Set i With Set i page AT90PWM1 Request for an Update Cycle With Set j End of Cycle 156. 133 ...
Page 134
... In enhanced mode, the output frequency is the average of the frame formed by the 16 consecu- tive cycles. f and f b1 Then the frequency resolution is divided by 16. In the example above, the resolution equals 25 Hz. AT90PWM1 134 Δ – = period in a PSC cycle and is given by the following formula: PSC is the output operating frequency ...
Page 135
... prime cycle corresponding cycle AT90PWM1 is the nearest base frequency above the wanted The f and f frequencies are evenly distrib ...
Page 136
... Figure 16-13. Enhanced Mode, Timing Diagram DT0 OT0 PSCOUTn0 PSCOUTn1 Period The supplementary step in counting to generate f in the frame according to the fractional divider. lated frame,” on page The waveform frequency is defined by the following equations the fractionel divider factor. AT90PWM1 136 ----------------------------- - = ---------------------------------------------------------------------- ( PSCn PSCnCycle ...
Page 137
... Digital 1 Filter 1 PFLTEnA CLK PSC (PFLTEnB) PISELnA (PISELnB) PELEVnA / PCAEnA 2 (PELEVnB) (PCAEnB) 4 PRFMnA3:0 (PRFMnB3:0) CLK PSC CLK PSC AT90PWM1 16.25.13page 161), PSCnIN0/1 input can act Input Processing (retriggering ...) PSC Core Output (Counter, Control PSCOUTn0 Waveform (PSCOUTn1) Generator, ...) (PSCOUT22) (PSCOUT23) 137 ...
Page 138
... The polarity of PSCn Input B is configurable thanks to a sense control block. PSCn Input B can be configured to do not act or to act on level or edge modes. PSCn Input B can be the Output of the analog comparator or the PSCINn input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases. AT90PWM1 138 On-Time 0 Dead-Time 0 Dead-Time 1 This exemple is given in “ ...
Page 139
... Dead-Time 0 This exemple is given in “Input Mode 1” in “ ramp mode” See Figure 16-20. for details. On level mode, it’s possible to use PSC to generate burst by using Input Mode 3 or Mode 4 ( See Figure 16-24. and Figure 16-25. for details.) AT90PWM1 On-Time 1 Dead-Time 0 On-Time 1 Dead-Time 1 Dead-Time 0 ...
Page 140
... PSC Input Filterring 16.8.4.2 Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit description in Section “PSC n Input A Control Register – PFRCnA”, page 16116.25.13. AT90PWM1 140 OFF BURST is running. So thanks to PSC Asynchronous Output Control bit ...
Page 141
... See “PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC” on page 1001b 148. Reserved : Do not use 1010b 1011b 1100b 1101b See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Dis- 1110b activate Output” on page 149. Reserved : Do not use 1111b AT90PWM1 141 ...
Page 142
... PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSC Input B event occurs, PSC releases PSCOUTn1, waits for PSC Input B inactive state and then jumps and executes DT0 plus OT0. AT90PWM1 142 DT0 ...
Page 143
... PSC Input B inactive state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com- pletely executed. 4378C–AVR–09/08 DT0 OT0 DT1 OT1 OT1 DT0 OT0 DT1 OT1 OT1 AT90PWM1 DT0 OT0 DT1 DT0 OT0 DT1 OT1 OT1 143 ...
Page 144
... When PSC Input B event occurs, PSC releases PSCnOUT1, jumps and executes DT0 plus OT0 plus DT1 while PSC Input active state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com- pletely executed. 16.12 PSC Input Mode 4: Deactivate outputs without changing timing. AT90PWM1 144 DT0 OT0 DT1 DT1 OT1 ...
Page 145
... Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 4378C–AVR–09/08 DT1 OT1 DT0 OT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 AT90PWM1 DT1 OT1 DT0 OT0 DT1 DT1 OT1 DT0 OT0 DT1 DT0 OT0 DT1 OT1 ...
Page 146
... OT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Note: Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. AT90PWM1 146 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 1. Software action is the setting of the PRUNn bit in PCTLn register. ...
Page 147
... The output frequency is modulated by the occurence of significative edge of retriggering input. The retrigger event is taken into account only if it occurs during the corresponding On-Time. 4378C–AVR–09/08 DT0 OT0 DT1 DT1 OT1 OT1 DT0 OT0 DT1 DT1 OT1 OT1 AT90PWM1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 147 ...
Page 148
... Only the significative edge of Retrigger/Fault input is taken into account. Figure 16-34. PSC behaviour versus PSCn Input B in Mode 9 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input B The retrigger event is taken into account only if it occurs during the corresponding On-Time. AT90PWM1 148 DT0 OT0 DT1 DT1 OT1 DT0 ...
Page 149
... Retrigger/Fault input is actve. The PSC runs at con- stant frequency. 4378C–AVR–09/08 DT0 OT0 DT1 OT1 OT1 DT0 OT0 DT1 OT1 OT1 AT90PWM1 DT0 OT0 DT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 ...
Page 150
... When using the Input Capture interrupt, the PICRn Register should be read as early in the inter- rupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. AT90PWM1 150 1 Ramp Mode 2 Ramp Mode ...
Page 151
... If POS23 bit in PSOC2 register is set, PSCOUT23 duplicates PSCOUT20. Figure 16-37. PSCOUT22 and PSCOUT23 Outptuts Waveform Generator A Waveform Generator B 4378C–AVR–09/08 Ramp 0 Ramp 1 POMV2A0 POMV2A1 POMV2B0 POMV2B1 0 1 POS22 Output POS23 Matrix 1 0 AT90PWM1 Ramp 2 Ramp 3 POMV2A2 POMV2A3 POMV2B2 POMV2B3 PSCOUT20 PSCOUT22 PSCOUT23 PSCOUT21 151 ...
Page 152
... The waveforms are center aligned in the Center Aligned mode if master and slaves are all with the same PSC period (which is the natural use). • The waveforms are edge aligned in the ramp mode Figure 16-38. PSC Run Synchronization AT90PWM1 152 4378C–AVR–09/08 ...
Page 153
... CLK I/O Figure 16-39. Clock selection PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source. PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the clock. 4378C–AVR–09/08 AT90PWM1 See “PSC 0 Control Register – PCTL0” 153 ...
Page 154
... Interrupts This section describes the specifics of the interrupt handling as performed in AT90PWM1. 16.24.1 List of Interrupt Vector Each PSC provides 2 interrupt vectors • PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs • PSCn CAPT (Capture Event): When enabled and one of the two following events occurs : retrigger, capture of the PSC counter or Synchro Error ...
Page 155
... Send signal on match with OCRnRA (during counting down of PSC). The 0 min value of OCRnRA must be 1. Send signal on match with OCRnRA (during counting up of PSC). The 1 min value of OCRnRA must synchronization signal 1 no synchronization signal AT90PWM1 POEN0B - POEN0A R/W ...
Page 156
... When this bit is set, I/O pin affected to PSCOUTn0 is connected to the PSC waveform generator A output and is set and clear according to the PSC operation. 16.25.3 Output Compare SA Register – OCRnSAH and OCRnSAL Bit Read/Write Initial Value 16.25.4 Output Compare RA Register – OCRnRAH and OCRnRAL Bit Read/Write Initial Value AT90PWM1 156 – – – – OCRnSA[7:0] W ...
Page 157
... PLOCK0 PMODE01 R/W R/W R/W R PFIFTY1 PALOCK1 PLOCK1 PMODE11 R/W R/W R/W R PFIFTY2 PALOCK2 PLOCK2 PMODE21 R/W R/W R/W R AT90PWM1 OCRnSB[11: OCRnRB[11: PMODE00 POP0 PCLKSEL0 - R/W R/W R/W R ...
Page 158
... Set this bit to enable the Output Matrix feature on PSC2 outputs. See 151. When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs. 16.25.10 PSC 0 Control Register – PCTL0 Bit Read/Write Initial Value AT90PWM1 158 PMODEn0 Description 0 One Ramp Mode 1 ...
Page 159
... Writing this bit to one starts the PSC 0. When set, this bit prevails over PARUN0 bit. 4378C–AVR–09/08 PPRE00 Description 0 No divider on PSC input clock 1 Divide the PSC input clock Divide the PSC input clock Divide the PSC clock by 64 AT90PWM1 159 ...
Page 160
... Bit 2 – PARUN2 : PSC 2 Autorun When this bit is set, the PSC 2 starts with PSC1. That means that PSC 2 starts : • when PRUN1 bit in PCTL1 register is set, • or when PARUN1 bit in PCTL1 is set and PRUN0 bit in PCTL0 register is set. AT90PWM1 160 ...
Page 161
... PCAEnA PISELnA PELEVnA PFLTEnA R/W R/W R/W R PCAEnB PISELnB PELEVnB PFLTEnB R/W R/W R/W R AT90PWM1 PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0 R/W R/W R/W R PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0 R/W R/W R/W R PFRCnA PFRCnB 161 ...
Page 162
... Initial Value 16.25.16 PSC 2 Input Capture Register – PICR2H and PICR2L Bit Read/Write Initial Value AT90PWM1 162 Description No action, PSC Input is ignored PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait PSC Input Mode 3: Stop signal, Execute Opposite while Fault active PSC Input Mode 4: Deactivate outputs without changing timing ...
Page 163
... Bit 0 – POMV2A0: Output Matrix Output A Ramp 0 This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 0 4378C–AVR–09/ POMV2B3 POMV2B2 POMV2B1 POMV2B0 R/W R/W R/W R AT90PWM1 POMV2A3 POMV2A2 POMV2A1 POMV2A0 R/W R/W R/W R POM2 163 ...
Page 164
... Bit Read/Write Initial Value • Bit 7 – POACnB : PSC n Output B Activity (not implemented on AT90PWM1) This bit is set by hardware each time the output PSCOUTn1 changes from from Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSC output doesn’t change due to a freezen external input signal. • ...
Page 165
... The last event which has generated an interrupt occured during ramp 1 1 The last event which has generated an interrupt occured during ramp 2 0 The last event which has generated an interrupt occured during ramp 3 1 The last event which has generated an interrupt occured during ramp 4 AT90PWM1 165 ...
Page 166
... Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM1 and peripheral devices or between several AVR devices. The AT90PWM1 SPI includes the following features: 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 167
... When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 51. SPI Pin Overrides Pin MOSI 4378C–AVR–09/08 Table 51. For more details on automatic port overrides, refer to 63. (1) Direction, Master SPI User Defined AT90PWM1 SHIFT ENABLE clkio “Alternate Port Direction, Slave SPI Input /4. 167 ...
Page 168
... DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB. AT90PWM1 168 (1) Direction, Master SPI ...
Page 169
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. The example code assumes that the part specific header file is included. AT90PWM1 169 ...
Page 170
... Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return data register */ return SPDR; } Note: AT90PWM1 170 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( The example code assumes that the part specific header file is included. ...
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... MISO,MOSI, SCK and SS. When the SPIPS bit is written to one,the SPI signals are directed on alternate SPI pins, MISO_A, MOSI_A, SCK_A and SS_A. When the SPIPS bit is written to zero, the SPI signals are directed on alternate SPI pins, MISO_A, MOSI_A, SCK_A and SS_A. AT90PWM1 PUD – ...
Page 172
... The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to functionality is summarized below: Table 53. CPHA Functionality • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 AT90PWM1 172 When the SPIPS bit is written to one,the SPI signals are directed on pins MISO,MOSI, SCK and SS. 7 ...
Page 173
... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the AT90PWM1 is also used for program memory and EEPROM down- loading or uploading. See verification. 4378C–AVR–09/08 ...
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... CPHA and CPOL. The SPI data transfer formats are shown in 17-3 and nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 52 Table 55. CPOL Functionality CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 17-3. SPI Transfer Format with CPHA = 0 AT90PWM1 174 SPD7 SPD6 SPD5 SPD4 R/W R/W ...
Page 175
... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 AT90PWM1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 LSB MSB 175 ...
Page 176
... The Analog Comparator compares the input values on the positive pin ACMPx and negative pin ACMPM. 18.1 Overview The AT90PWM1 features three fast analog comparators. Each comparator has a dedicated input on the positive input, and the negative input can be con- figured as: • a steady value among the 4 internal reference levels defined by the Vref selected thanks to the REFS1:0 bits in ADMUX register. • ...
Page 177
... ADC multiplexer output: see Table 63 on page 2. Refer to Figure 3-1 on page 2 and for Analog Comparator pin placement. 3. The voltage on Vref is defined AC0EN AC0IE AC0IS1 R/W R/W R AT90PWM1 (1)(2) 195. 62 ”ADC Voltage Reference Selection” on page 194 AC0IS0 - AC0M2 AC0M1 R/W - R/W R ...
Page 178
... Clear this bit to disable the analog comparator 2. • Bit 6– AC2IE: Analog Comparator 2 Interrupt Enable bit Set this bit to enable the analog comparator 2 interrupt. Clear this bit to disable the analog comparator 2 interrupt. • Bit 5, 4– AC2IS1, AC2IS0: Analog Comparator 2 Interrupt Select bit AT90PWM1 178 Table 56. AC0IS0 ...
Page 179
... AC2M0 Description 0 0 “Vref”/6. “Vref”/3. “Vref”/2. “Vref”/1. Analog Comparator Negative Input (ACMPM pin DAC result 1 0 Reserved 1 1 Reserved ACCKDIV AC2IF AC0IF R/W R/W R AT90PWM1 AC2O AC0O - ACSR 179 ...
Page 180
... The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. AT90PWM1 180 7 ...
Page 181
... Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The AT90PWM1 features a 10-bit successive approximation ADC. The ADC is connected to an 15-channel Analog Multiplexer which allows eleven single-ended input. The single-ended volt- age inputs refer to 0V (GND). The device also supports 2 differential voltage input combinations which are equipped with a programmable gain stage, providing amplification steps of 14dB (5x (10x (20x), or 32dB (40x) on the differential input voltage before the A/D conversion ...
Page 182
... Figure 19-1. Analog to Digital Converter Block Schematic AT90PWM1 182 4378C–AVR–09/08 ...
Page 183
... Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 4378C–AVR–09/08 AT90PWM1 or an internal 2.56V reference voltage may be con- CC 183 ...
Page 184
... CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. AT90PWM1 184 ADTS[2:0] ADIF ...
Page 185
... Update Cycle Number ADC Clock ADSC ADIF ADCH ADCL Sample & Hold MUX and REFS Update AT90PWM1 “Changing Channel or Reference Table First Conversion Conversion Sample & Hold Complete One Conversion Next Conversion ...
Page 186
... ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. AT90PWM1 186 1 2 ...
Page 187
... ADC. Single REF will result in codes close to 0x3FF. V REF , internal 2.56V reference, or external AREF pin. CC AT90PWM1 can be selected as REF ) through an internal amplifier. In either case, the BG can REF is a high REF and 2 ...
Page 188
... Signal components higher than the Nyquist frequency (f kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. AT90PWM1 188 Table 23-5 on page 245. mode must be selected and the ADC conversion complete interrupt must be enabled ...
Page 189
... I IH ADCn analog ground plane, and keep them well away from high-speed switching digital tracks. pin on the device should be connected to the digital network as shown in Figure switch while a conversion is in progress. AT90PWM1 1..100 kΩ S supply voltage via CC 19-9 ...
Page 190
... LSB). Ideal value: 0 LSB. Figure 19-10. Offset Error • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB AT90PWM1 190 Output Code Offset Error ). This offset residue ...
Page 191
... Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. 4378C–AVR–09/08 Output Code Output Code AT90PWM1 Gain Error Ideal ADC Actual ADC V Input Voltage ...
Page 192
... ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is posi- tive. Figure 19-14 Table 82 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is selected with a reference voltage of V AT90PWM1 192 Output Code 0x3FF 1 LSB ...
Page 193
... V /GAIN 0x201 REF - V /GAIN 0x200 REF ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 AT90PWM1 0 V REF Corresponding decimal value 511 511 510 ... ...
Page 194
... ADC Register Description The ADC of the AT90PWM1 is controlled through 3 different registers. The ADCSRA and The ADCSRB registers which are the ADC Control and Status registers, and the ADMUX which allows to select the Vref source and the channel to be converted. The conversion result is stored on ADCH and ADCL register which contain respectively the most significant bits and the less significant bits ...
Page 195
... Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect. The first conversion performs the initialization of the ADC. In order to start a conversion on an amplified channel with the AT90PWM1, use the ADCS bit in ADCSRA register. 4378C–AVR–09/08 Table 63 ...
Page 196
... In accordance with the Table 19-1, these 3 bits select the interrupt event which will generate the trigger of the start of conversion. The start of conversion will be generated by the rising edge of the selected interrupt flag whether the interrupt is enabled or not. In case of trig on PSCnASY AT90PWM1 196 197. ...
Page 197
... AT90PWM1 ADTS0 Description 0 Free Running Mode 1 Analog Comparator 0 0 External Interrupt Request 0 1 Timer/Counter0 Compare Match 0 Timer/Counter0 Overflow 1 Timer/Counter1 Compare Match B 0 Timer/Counter1 Overflow 1 Timer/Counter1 Capture Event (1) 0 PSC0ASY Event ...
Page 198
... Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the result thanks to the ADLAR bit in the ADCSRA register. Like this sufficient to only read ADCH to have the conversion result. 19.8.4.1 ADLAR = 0 Bit Read/Write Initial Value AT90PWM1 198 ADC Auto Trigger Source Selection for amplified conversions ADTS2 ADTS1 ...
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... Amplifier The AT90PWM1 features one differential amplified channel with programmable 5, 10, 20, and 40 gain stage. On AT90PWM1, the amplifier has been improved in order to speed-up the conversion time.The proposed improvement takes advantage of the amplifier characteristics to ensure a conversion in less time. In order to have a better understanding of the functioning of the amplifier synchronization, a tim- ...
Page 200
... Figure 19-15. Amplifier synchronization timing diagram nal to be measu red PSC PS Cn_ASY Block AMPLI_clk (Sync Clock) CK ADC ADSC ADC ADC Activity AT90PWM1 200 With change on analog input signal Delta V ADC Conv ADC Sampling ADC Result Ready 4th stable sample Valid sample ADC ...