ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 101

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

9. Module Description
9.1
9.1.1
8111C–MCU Wireless–09/09
Receiver (RX)
Overview
The AT86RF231 receiver is split into an analog radio front end and a digital base band proces-
sor (RX BBP), see
Figure 9-1.
The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down
converted to an intermediate frequency by a mixer. Channel selectivity is performed using an
integrated band pass filter (BPF). A limiting amplifier (Limiter) provides sufficient gain to over-
come the DC offset of the succeeding analog-to-digital converter (ADC) and generates a digital
RSSI signal. The ADC output signal is sampled and processed further by the digital base band
receiver (RX BBP).
The RX BBP performs additional signal filtering and signal synchronization. The frequency offset
of each frame is calculated by the synchronization unit and is used during the remaining receive
process to correct the offset. The receiver is designed to handle frequency and symbol rate devi-
ations up to ±120 ppm, caused by combined receiver and transmitter deviations. For details
refer to
nal is demodulated and the data are stored in the Frame Buffer.
In Basic Operating Mode, refer to
of a frame is indicated by an interrupt IRQ_2 (RX_START). Accordingly its end is signalized by
an interrupt IRQ_3 (TRX_END). Based on the quality of the received signal a link quality indica-
tor (LQI) is calculated and appended to the frame, refer to
(LQI)” on page
status information like ED value (register 0x07, ED_LEVEL) and FCS correctness (register
0x06, PHY_RSSI).
Beyond these features the Extended Operating Mode of the AT86RF231 supports address filter-
ing and pending data indication. For details refer to
page
RFP
RFN
47.
Section 12.5 “General RF Specifications” on page 158
LNA
Receiver Block Diagram
99. Additional signal processing is applied to the frame data to provide further
Figure 9-1 on page
PPF
LO
Section 7.1 “Basic Operating Mode” on page
BPF
101.
Limiter
AGC
Analog Domain
Section 7.2 “Extended Operating Mode” on
ADC
RSSI
Section 8.6 “Link Quality Indication
parameter 12.5.8. Finally the sig-
RX BBP
Frame
Buffer
Control, Registers
AT86RF231
Digital Domain
33, the reception
SPI
101
SPI
µC
I/F
I/F