ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 104

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

9.2
9.2.1
9.2.2
9.2.3
9.2.4
8111C–MCU Wireless–09/09
Transmitter (TX)
Overview
Frame Transmit Procedure
Configuration
TX Power Ramping
The AT86RF231 transmitter consists of a digital base band processor (TX BBP) and an analog
radio front end, see
Figure 9-2.
The TX BBP reads the frame data from the Frame Buffer and performs the bit-to-symbol and
symbol-to-chip mapping as specified by IEEE 802.15.4 in section 6.5.2. The O-QPSK modula-
tion signal is generated and fed into the analog radio front end.
The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to the RF
signal, which is amplified by the power amplifier (PA). The PA output is internally connected to
bidirectional differential antenna pins (RFP, RFN), so that no external antenna switch is needed.
The frame transmit procedure including writing PSDU data in the Frame Buffer and initiating a
transmission is described in
Transmit Procedure.
The maximum output power of the transmitter is typically +3 dBm. The output power can be con-
figured via register bits TX_PWR (register 0x05, PHY_TX_PWR). The output power of the
transmitter can be controlled over a range of 20 dB.
A transmission can be started from PLL_ON or TX_ARET_ON state by a rising edge of pin
SLP_TR or by writing TX_START command to register bits TRX_CMD (register 0x02,
TRX_STATE).
To optimize the output power spectral density (PSD), the PA buffer and PA are enabled sequen-
tially. This is illustrated by a timing example using default settings, shown in
105. In this example the transmission is initiated with the rising edge of pin 11 (SLP_TR). The
radio transceiver state changes from PLL_ON to BUSY_TX. The modulation starts 16 µs after
SLP_TR.
RFP
DIG3/4
RFN
PA
Transmitter Block Diagram
Figure 9-2 on page
Buf
Section 10.2 “Frame Transmit Procedure” on page
Output Power Control
Ext. RF front-end and
PLL – TX Modulation
104.
Analog Domain
TX Data
TX BBP
Frame
Buffer
Control, Registers
AT86RF231
Figure 9-3 on page
Digital Domain
SPI
127, Frame
104
SPI
µC
I/F
I/F