ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 118

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

9.6.5
8111C–MCU Wireless–09/09
Bit
+0x03
Read/Write
Initial Value
Register Description
R/W
7
0
PAD_IO
R/W
6
0
Note:
Register 0x03 (TRX_CTRL_0):
The TRX_CTRL_0 register controls the drive current of the digital output pads and the CLKM
clock rate. It is recommended to use the lowest value for the drive current to reduce the current
consumption and the emission of signal harmonics.
• Bit [7:6] - PAD_IO
Refer to
• Bit [5:6] - PAD_IO_CLKM
These register bits set the output driver current of pin CLKM. It is recommended to reduce the
current capability to PAD_IO_CLKM = 0 (2 mA) if possible. This reduces power consumption
and spurious emissions.
Table 9-12.
• Bit 3 - CLKM_SHA_SEL
Register bit CLKM_SHA_SEL defines if a new clock rate, defined by CLKM_CTRL, is set imme-
diately or after the next SLEEP cycle.
Table 9-13.
Register Bit
PAD_IO_CLKM
Register Bit
CLKM_SHA_SEL
• During reset procedure, see
• For example, if the CLKM clock rate is configured to 16 MHz the CLKM clock rate remains at 16 MHz
shadowed. Although the clock setting of CLKM remains after reset, a read access to register bits
CLKM_CTRL delivers the reset value 1. For that reason it is recommended to write the previous
configuration (before reset) to register bits CLKM_CTRL (after reset) to align the radio transceiver
behavior and register configuration. Otherwise the CLKM clock rate is set back to the reset value (1
MHz) after the next SLEEP cycle.
after a reset, however the register bits CLKM_CTRL are set back to 1. Since CLKM_SHA_SEL reset
value is 1, the CLKM clock rate changes to 1 MHz after the next SLEEP cycle if the CLKM_CTRL
setting is not updated after reset.
Section 1.3 “Digital Pins” on page
R/W
5
0
PAD_IO_CLKM
CLKM Driver Strength
CLKM Clock Rate Update Scheme
R/W
4
1
Value
Value
Section 7.1.2.8 “RESET State” on page
0
1
2
3
0
1
CLKM_SHA_SEL
Description
2 mA
4 mA
6 mA
8 mA
Description
CLKM clock rate change appears immediately
CLKM clock rate change appears after SLEEP cycle
R/W
3
1
7.
R/W
2
0
CLKM_CTRL
R/W
1
0
37, register bits CLKM_CTRL are
AT86RF231
R/W
0
1
TRX_CTRL_0
118