ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 126

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

10. Radio Transceiver Usage
10.1
8111C–MCU Wireless–09/09
Frame Receive Procedure
This section describes basic procedures to receive and transmit frames using the AT86RF231.
For a detailed programming description refer to reference [6].
A frame reception comprises of two actions: The PHY listens for, receives and demodulates the
frame to the Frame Buffer and signalizes the reception to the microcontroller. After or while that
the microcontroller read the available frame data from the Frame Buffer via the SPI interface.
While in state RX_ON or RX_AACK_ON the radio transceiver searches for incoming frames on
the selected channel. Assuming the appropriate interrupts are enabled, a detection of an
IEEE 802.15.4 compliant frame is indicated by interrupt IRQ_2 (RX_START) first. The frame
reception is completed when issuing interrupt IRQ_3 (TRX_END).
Different Frame Buffer read access scenarios are recommended for:
Waiting for IRQ_3 (TRX_END) interrupt before starting a Frame Buffer read access is recom-
mended for operations considered to be none time critical.
the frame receive procedure using IRQ_3 (TRX_END).
Figure 10-1. Transactions between AT86RF231 and Microcontroller during Receive
Critical protocol timing could require starting the Frame Buffer read access after interrupt
IRQ_2 (RX_START). The first byte of the frame data can be read 32 µs after the
IRQ_2 (RX_START) interrupt. The microcontroller must ensure to read slower than the frame is
received. Otherwise a Frame Buffer under run occurs, IRQ_6 (TRX_UR) is issued, and the
frame data may be not valid. To avoid this, the Frame Buffer read access can be controlled by
using a Frame Buffer Empty indicator, refer to
page
• Non-time critical applications
• Time-critical applications
152.
Read IRQ status, pin 24 (IRQ) deasserted
Read IRQ status, pin 24 (IRQ) deasserted
Read frame data (Frame Buffer access)
IRQ issued (IRQ_2)
IRQ issued (IRQ_3)
read access starts after IRQ_3 (TRX_END)
read access starts after IRQ_2 (RX_START)
Section 11.7 “Frame Buffer Empty Indicator” on
Figure 10-1 on page 126
AT86RF231
illustrates
126