ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 157

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

12.3
Table 12-3.
Note:
12.4
Table 12-4.
8111C–MCU Wireless–09/09
No.
12.3.1
12.3.2
12.3.3
12.3.4
No.
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
12.4.6
12.4.7
12.4.8
12.4.9
12.4.10
12.4.11
12.4.12
12.4.13
12.4.14
12.4.15
Digital Pin Characteristics
1. The capacitive load should not be larger than 50 pF for all I/Os when using the default driver strength settings, refer to
Digital Interface Timing Characteristics
Symbol
V
V
V
V
tion 1.3.1 “Driver Strength Settings” on page
Symbol
IH
IL
OH
OL
f
f
async
sync
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
Digital Pin Characteristics
Digital Interface Timing Characteristics
1
2
3
4
5
6
7
8
8
9
Parameter
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Parameter
SCLK frequency
SCLK frequency
/SEL low to MISO active
SCLK to MISO out
MOSI setup time
MOSI hold time
LSB last byte to MSB next byte
/SEL high to MISO tri state
SLP_TR pulse width
SPI idle time
SPI idle time
Last SCLK to /SEL high
Reset pulse width
SPI access latency after reset
AES core cycle time
(SEL rising to falling edge)
(SEL rising to falling edge)
.Test Conditions: T
Test Conditions: T
(1)
(1)
(1)
(1)
OP
OP
= 25°C, V
= 25°C (unless otherwise stated)
Condition
For all output driver strengths defined
in TRX_CTRL_0
For all output driver strengths defined
in TRX_CTRL_0
7. Generally, large load capacitances increase the overall current consumption.
Condition
synchronous operation
asynchronous operation
data hold time
TX start trigger
SPI read/write, standard SRAM
and Frame Buffer access modes,
Idle time between consecutive SPI
accesses
SPI Fast SRAM read/write access
mode, refer to
Idle time between consecutive SPI
accesses
10 clock cycles at 16 MHz
10 clock cycles at 16 MHz
DD
= 3.0V, C
Section
L
= 50 pF (unless otherwise stated).
11.1.5,
V
V
DD
DD
Min.
250
Min.
62.5
250
500
625
625
- 0.4
- 0.4
10
10
10
(2)
Typ.
250
24
Typ.
AT86RF231
Note
Max
180
7.5
10
Max
0.4
0.4
8
(1)
Units
V
V
V
V
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Sec-
157