ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 20

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

Figure 6-6.
6.2.2
Figure 6-7.
8111C–MCU Wireless–09/09
MOSI
MISO
/SEL
SCLK
MOSI
MISO
0
Register Write Access
Frame Buffer Access Mode
byte 1 (command byte)
0
PHY_STATUS
WRITE COMMAND
1
Example SPI Sequence - Register Access Mode
Packet Structure - Frame Read Access
PHY_STATUS
reserved[4:0]
Figure 6-5.
Each register access must be terminated by setting /SEL = H.
Figure 6-6 on page 20
and read respectively.
The 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one
IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed descrip-
tion of the Frame Buffer can be found in
to the IEEE 802.15.4 frame format can be found in
Frame Buffer read and write accesses are used to read or write frame data (PSDU and addi-
tional information) from or to the Frame Buffer. Each access starts with /SEL = L followed by a
command byte on MOSI. If this byte indicates a frame read or write access, the next byte
PHR[7:0] indicates the frame length followed by the PSDU data, see
Figure 6-8 on page
On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO starting
with the second byte. After the PSDU data, one more byte is transferred containing the link qual-
ity indication (LQI) value of the received frame, for details refer to
Indication (LQI)” on page
Buffer read access.
2006 Frame Format” on page
byte 2 (data byte)
PHR[7:0]
MOSI
MISO
WRITE DATA
XX
Packet Structure - Register Write Access
XX
21.
1
illustrates a typical SPI sequence for a register access sequence for write
byte 1 (command byte)
1
99.
PHY_STATUS
byte 3 (data byte)
Figure 6-7 on page 20
79.
PSDU[7:0]
ADDRESS[5:0]
XX
Section 9.3 “Frame Buffer” on page
Register Read Access
READ COMMAND
PHY_STATUS
Section 8.1 “Introduction - IEEE 802.15.4 -
illustrates the packet structure of a Frame
byte n-1 (data byte)
PSDU[7:0]
WRITE DATA[7:0]
byte 2 (data byte)
XX
XX
READ DATA
Figure 6-7 on page 20
Section 8.6 “Link Quality
AT86RF231
XX
107. An introduction
byte n (data byte)
LQI[7:0]
XX
and
20