ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 22

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

Figure 6-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4 byte PSDU
6.2.3
Figure 6-11. Packet Structure - SRAM Read Access
8111C–MCU Wireless–09/09
/SEL
SCLK
MOSI
MISO
MOSI
MISO
0
SRAM Access Mode
byte 1 (command byte)
0
PHY_STATUS
0
PHY_STATUS
COMMAND
reserved[4:0]
Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6
(TRX_UR). For further details, refer to
Notes
The SRAM access mode allows accessing dedicated bytes within the Frame Buffer. This may
reduce the SPI traffic.
The SRAM access mode is useful, for instance, if a transmit frame is already stored in the Frame
Buffer and dedicated bytes (e.g. sequence number, address field) need to be replaced before
retransmitting the frame. Furthermore, it can be used to access only the LQI value after frame
reception. A detailed description of the user accessible frame content can be found in
9.3 “Frame Buffer” on page
Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the com-
mand byte and must indicate an SRAM access mode according to the definition in
page
space is 0x00 to 0x7F for radio transceiver receive or transmit operations.
On SRAM read access, one or more bytes of read data are transferred on MISO starting with the
third byte of the access sequence (see
• The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by
• To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to
• It is not possible to retransmit received frames without a Frame Buffer read and write access
• For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode
new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no
frame was received in the meanwhile.
Section 11.8 “Dynamic Frame Buffer Protection” on page
cycle.
(TX_ARET) refer to
CSMA-CA Retry” on page
0
19. The following byte indicates the start address of the write or read access. The address
XX
PHR
ADDRESS[6:0]
byte 2 (address)
XX
PSDU 1
XX
Section 7.2.4 “TX_ARET_ON - Transmit with Automatic Retry and
107.
byte 3 (data byte)
64.
DATA[7:0]
XX
PSDU 2
XX
Section 9.3 “Frame Buffer” on page
Figure 6-11 on page
PSDU 3
XX
byte n-1 (data byte)
DATA[7:0]
22).
154.
XX
PSDU 4
XX
AT86RF231
107.
byte n (data byte)
DATA[7:0]
XX
Table 6-2 on
Section
22