ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 23

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

Figure 6-12. Packet Structure - SRAM Write Access
Figure 6-13. Example SPI Sequence - SRAM Read Access of a 5 byte Data Package
Figure 6-14. Example SPI Sequence - SRAM Write Access of a 5 byte Data Package
8111C–MCU Wireless–09/09
MOSI
MISO
/SEL
SCLK
MOSI
MISO
/SEL
SCLK
MOSI
MISO
0
byte 1 (command byte)
1
PHY_STATUS
PHY_STATUS
0
PHY_STATUS
COMMAND
COMMAND
reserved[4:0]
On SRAM write access, one or more bytes of write data are transferred on MOSI starting with
the third byte of the access sequence (see
On SRAM read or write accesses do not attempt to read or write bytes beyond the SRAM buffer
size.
As long as /SEL = L, every subsequent byte read or byte write increments the address counter
of the Frame Buffer until the SRAM access is terminated by /SEL = H.
Figure 6-13 on page 23
SRAM access to read and write a data package of 5-byte length respectively.
Notes
• The SRAM access mode is not intended to be used as an alternative to the Frame Buffer
• If the SRAM access mode is used to read PSDU data, the Frame Buffer contains all PSDU
• Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the
access modes (see
data except the frame length byte (PHR). The frame length information can be accessed only
using Frame Buffer access.
SRAM access mode, for further details refer to
109.
0
ADDRESS
ADDRESS
XX
XX
ADDRESS[6:0]
byte 2 (address)
XX
DATA 1
DATA 1
XX
XX
Section 6.2.2 “Frame Buffer Access Mode” on page
and
Figure 6-14 on page 23
byte 3 (data byte)
DATA[7:0]
XX
DATA 2
DATA 2
XX
XX
Figure 6-12 on page
DATA 3
DATA 3
XX
Section 9.3.3 “Interrupt Handling” on page
XX
illustrate an example SPI sequence of a
byte n-1 (data byte)
DATA[7:0]
XX
DATA 4
DATA 4
23).
XX
XX
AT86RF231
20).
byte n (data byte)
DATA 5
DATA 5
DATA[7:0]
XX
XX
XX
23