ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 36

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

7.1.2.4
7.1.2.5
7.1.2.6
8111C–MCU Wireless–09/09
PLL_ON - PLL State
RX_ON and BUSY_RX - RX Listen and Receive State
RX_ON_NOCLK - RX Listen State without CLKM
Entering the TRX_OFF state from P_ON, SLEEP, or RESET state is indicated by interrupt
IRQ_4 (AWAKE_END).
Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG)
first. After the voltage regulator has been settled, the PLL frequency synthesizer is enabled.
When the PLL has been settled at the receive frequency to a channel defined by register bits
CHANNEL (register 0x08, PHY_CC_CCA), a successful PLL lock is indicated by issuing an
interrupt IRQ_0 (PLL_LOCK).
If an RX_ON command is issued in PLL_ON state, the receiver is immediately enabled. If the
PLL has not been settled before the state change nevertheless takes place. Even if the register
bits TRX_STATUS (register 0x01, TRX_STATUS) indicates RX_ON, actual frame reception can
only start once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
In RX_ON state the receiver blocks and the PLL frequency synthesizer are enabled.
The AT86RF231 receive mode is internally separated into RX_ON state and BUSY_RX state.
There is no difference between these states with respect to the analog radio transceiver cir-
cuitry, which are always turned on. In both states the receiver and the PLL frequency
synthesizer are enabled.
During RX_ON state the receiver listens for incoming frames. After detecting a valid synchroni-
zation header (SHR), the AT86RF231 automatically enters the BUSY_RX state. The reception
of a valid PHY header (PHR) generates an IRQ_2 (RX_START) and receives and demodulates
the PSDU data.
During PSDU reception the frame data are stored continuously in the Frame Buffer until the last
byte was received. The completion of the frame reception is indicated by an interrupt IRQ_3
(TRX_END) and the radio transceiver reenters the state RX_ON. At the same time the register
bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see
Section 8.2 “Frame Check Sequence (FCS)” on page
Received frames are passed to the frame filtering unit, refer to
on page
Section 7.2.1) of a frame matches to the expected addresses, which is further dependent on the
addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to
rupt Logic” on page
(Short address, PAN-ID and IEEE address). Frame filtering is available in Basic and Extended
Operating Mode, refer to
Leaving state RX_ON is only possible by writing a state change command to register bits
TRX_CMD in register 0x02 (TRX_STATE).
If the radio transceiver is listening for an incoming frame and the microcontroller is not running
an application, the microcontroller may be powered down to decrease the total system power
consumption. This specific power-down scenario for systems running in clock synchronous
mode (see
using the state RX_ON_NOCLK.
61. If the content of the MAC addressing fields (refer to IEEE 802.15.4-2006,
Section 6. “Microcontroller Interface” on page
29. The expected address values are to be stored in registers 0x20 - 0x2B
Section 7.2.3.5 “Frame Filtering” on page
85).
16), is supported by the AT86RF231
Section 7.2.3.5 “Frame Filtering”
61.
AT86RF231
Section 6.6 “Inter-
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