ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 43

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

Table 7-1.
Table 7-2.
8111C–MCU Wireless–09/09
No
No
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TR10
TR11
TR12
TR13
TR14
TR15
TR16
TR17
TR18
TR19
TR20
TR21
TR22
TR23
TR24
TR25
TR26
TR27
TR28
TR29
State Transition Timing (Continued)
Analog Block Initialization and Settling Time
Block
XOSC
FTN
DVREG
AVREG
PLL, initial
PLL settling
PLL, CF cal
PLL, DCU cal
PLL, RX
PLL, TX
RSSI, update
ED
SHR, sync
CCA
Random value
PLL_ON
BUSY_TX
All states
RESET
Various
states
⇒
⇒
Transition
The state transition timing is calculated based on the timing of the individual blocks shown in
Figure 7-3 on page 39
ating temperature, minimum supply voltage, and device parameter variations.
RX
TX
⇒
⇒
⇒
⇒
⇒
Time [µs], (type)
BUSY_TX
PLL_ON
TRX_OFF
TRX_OFF
PLL_ON
330
110
60
60
11
35
96
Time [µs], (type)
140
140
16
32
6
2
1
to
Time [µs], (max)
Figure 7-7 on page
16
32
37
1
1
1000
1000
1000
155
25
24
Comments
When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START
first symbol transmission is delayed by 16 µs delay (PLL
settling and PA ramp up)
PLL settling time from TX_BUSY to PLL_ON state
Using TRX_CMD = FORCE_TRX_OFF (see register 0x02,
TRX_STATE),
Not valid for SLEEP state
Valid for P_ON or SLEEP state
Using TRX_CMD = FORCE_PLL_ON (see register 0x02,
TRX_STATE),
Not valid for SLEEP, P_ON, RESET, TRX_OFF and *_NOCLK
Comment
Leaving SLEEP state, depends on crystal Q factor and
load capacitor
FTN tuning time fixed
Depends on external bypass capacitor at DVDD
(CB3 = 1 µF nom., 10 µF worst case), depends on V
Depends on external bypass capacitor at AVDD
(CB1 = 1 µF nom, 10 µF worst case), depends on V
PLL settling time TRX_OFF
AVREG settling time
Settling time between channels switch
PLL center frequency calibration, refer to
PLL DCU calibration, refer to
Maximum PLL settling time RX
Maximum PLL settling time TX
RSSI update period in receive states, refer to
ED measurement period, refer to
Typical SHR synchronisation period, refer to
CCA measurement period, refer to
Random value update period, refer to
41. The worst case values include maximum oper-
⇒
Section 9.7.4
PLL_ON, including 60 µs
⇒
⇒
RX
TX
Section 8.4.2
Section 8.5.2
AT86RF231
Section 11.2.1
Section 9.7.4
Section 8.4.2
Section 8.3.2
DD
DD
43