ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 54

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

7.2.3.1
8111C–MCU Wireless–09/09
Description of RX_AACK Configuration Bits
Overview
Table 7-5 on page 54
transaction. For address filtering it is further required to setup address registers to match to the
expected address.
Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior to switching to
RX_AACK mode.
A graphical representation of various operating modes is illustrated in
Table 7-5.
The usage of the RX_AACK configuration bits for various operating modes of a node is
explained in the following sections. Configuration bits not mentioned in the following two sec-
tions should be set to their reset values according to
All registers mentioned in
mary” on page
Note, that the general behavior of the "AT86RF231 Extended Feature Set",
“AT86RF231 Extended Feature Set” on page
0x20,0x21
0x22,0x23
Register
Address
...........
0x0C
0x2C
0x2B
0x2E
0x2E
0x2E
0x2E
0x24
0x17
0x17
0x17
0x17
Overview of RX_AACK Configuration Bits
68.
Register
Bits
7:6
7
1
2
4
5
0
3
4
5
summarizes all register bits which affect the behavior of an RX_AACK
Table 7-5 on page 54
Register Name
SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0
........
IEEE_ADDR_7
RX_SAFE_MODE
AACK_PROM_MODE
AACK_ACK_TIME
AACK_UPLD_RES_FT
AACK_FLTR_RES_FT
SLOTTED_OPERATION
AACK_I_AM_COORD
AACK_DIS_ACK
AACK_SET_PD
AACK_FVN_MODE
128, settings:
are described in
Description
Set node addresses
Protect buffer after frame receive
Support promiscuous mode
Change auto acknowledge start time
Enable reserved frame type reception, needed
to receive non-standard compliant frames
Filter reserved frame types like data frame
type, needed for filtering of non-standard
compliant frames
If set, acknowledgment transmission has to be
triggered by pin 11 (SLP_TR)
If set, the device is a PAN coordinator
Disable generation of acknowledgment
Set frame pending subfield in Frame Control
Field (FCF), refer to
Controls the ACK behavior, depending on FCF
frame version number
Table 14-1 on page
Section 7.2.6 “Register Sum-
Figure 7-9 on page
Section 8.1.2.2
170.
AT86RF231
Section 11.
53.
54