ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 73

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

8111C–MCU Wireless–09/09
Bit
+0x2C
Read/Write
Reset Value
R/W
7
0
MAX_FRAME_RETRIES
R/W
Register 0x2C (XAH_CTRL_0):
Register 0x2C (XAH_CTRL_0) is a control register for Extended Operating Mode.
• Bit [7:4] - MAX_FRAME_RETRIES
The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to
retransmit a frame, when it was not acknowledged by the recipient, before the transaction gets
cancelled.
• Bit [3:1] - MAX_CSMA_RETRIES
MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-
CA procedure before the transaction gets cancelled. According IEEE 802.15.4 the valid range of
MAX_CSMA_RETRIES is [0, 1, …, 5].
A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without per-
forming CSMA-CA. This may especially be required for slotted acknowledgement operation.
MAX_CSMA_RETRIES = 6 is reserved.
• Bit 0 - SLOTTED_OPERATION
Using RX_AACK mode in networks operating in beacon or slotted mode, refer to IEEE 802.15.4
2006, section 5.5.1, register bit SLOTTED_OPERATION indicates that acknowledgement
frames are to be sent on back-off slot boundaries (slotted acknowledgement).
If this register bit is set the acknowledgement frame transmission has to be initiated by the
microcontroller using the rising edge of pin 11 (SLP_TR). This waiting state is signaled in sub
register TRAC_STATUS (register 0x02, TRX_STATE) with value SUCCESS_WAIT_FOR_ACK.
Table 7-18.
Register 0x2D (CSMA_SEED_0):
6
0
Bit
+0x2D
Read/Write
Reset Value
Register Bit
SLOTTED_OPERATION
R/W
5
1
Register Bit Slotted Acknowledgement Operation
R/W
7
1
R/W
4
R/W
1
6
1
Value
0
1
R/W
5
1
R/W
3
1
State Description
The radio transceiver operates in unslotted mode. An
acknowledgment frame is automatically sent if requested.
Refer to
acknowledgement frame has to be controlled by the
microcontroller.
MAX_CSMA_RETRIES
CSMA_SEED_0[7:0]
R/W
4
0
Section
R/W
2
0
R/W
7.2.3.6. The transmission of an
3
1
R/W
1
0
R/W
2
0
SLOTTED_OPERATION
R/W
1
1
R/W
0
0
AT86RF231
R/W
0
0
CSMA_SEED_0
XAH_CTRL_0
73