ATmega1284RZAP Atmel Corporation, ATmega1284RZAP Datasheet - Page 138

• Manufacturer Part Number: ATmega1284RZAP
• Manufacturer: Atmel Corporation

Specifications of ATmega1284RZAP

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: No
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: No
• External Pa Control: No
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 16.0
• Transmit Current Consumption (ma): 17.0
• Link Budget (dbm): 104

14.11.11 TIFR3 – Timer/Counter3 Interrupt Flag Register
8059D–AVR–11/09
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4:3 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOV1 Flag is set when the timer overflows. Refer to
Flag behavior when using another WGMn3:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
• Bit 7:6 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 5 – ICF3: Timer/Counter3, Input Capture Flag
This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF3 Flag is set when the coun-
ter reaches the TOP value.
ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF3 can be cleared by writing a logic one to its bit location.
• Bit 4:3 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
Bit
0x18 (0x38)
Read/Write
Initial Value
R
7
–
0
R
6
–
0
ICF3
R/W
5
0
R
4
–
0
R
3
–
0
Table 14-5 on page 133
OCF3B
R/W
2
0
ATmega1284P
OCF3A
R/W
1
0
TOV3
R/W
0
0
for the TOV1
TIFR3
138