ATmega1284RZAP Atmel Corporation, ATmega1284RZAP Datasheet - Page 173

• Manufacturer Part Number: ATmega1284RZAP
• Manufacturer: Atmel Corporation

Specifications of ATmega1284RZAP

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: No
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: No
• External Pa Control: No
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 16.0
• Transmit Current Consumption (ma): 17.0
• Link Budget (dbm): 104

17.4.1
8059D–AVR–11/09
Internal Clock Generation – The Baud Rate Generator
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 17-2
Figure 17-2. Clock Generation Logic, Block Diagram
Signal description:
operation.
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRLn Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
Table 17-1 on page 174
for calculating the UBRRn value for each mode of operation using an internally generated clock
source.
Note:
osc
), is loaded with the UBRRn value each time the counter has counted down to zero or when
txclk
rxclk
xcki
xcko
f
BAUD
OSC
DDR_XCK
1. The baud rate is defined to be the transfer rate in bit per second (bps)
XCK
Pin
shows a block diagram of the clock generation logic.
xcko
xcki
OSC
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
Baud rate (in bits per second, bps)
Down-Counter
Prescaling
contains equations for calculating the baud rate (in bits per second) and
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/2
Figure 17-2 on page
osc
/(UBRRn+1)). The Transmitter divides the
/4
/2
ATmega1284P
DDR_XCK
173.
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
173