ATmega1284RZAP Atmel Corporation, ATmega1284RZAP Datasheet - Page 49
ATmega1284RZAP
Manufacturer Part Number
ATmega1284RZAP
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1284RZAP
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
0.25
Antenna Diversity
No
External Pa Control
No
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
16.0
Transmit Current Consumption (ma)
17.0
Link Budget (dbm)
104
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9.1.2
8059D–AVR–11/09
Power-on Reset
Figure 9-1.
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in
V
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V
CC
is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
BODLEVEL [2..0]
CC
decreases below the detection level.
”System and Reset Characteristics” on page
Reset Logic
Pull-up Resistor
JTAG Reset
Register
FILTER
SPIKE
CC
CKSEL[3:0]
rise. The RESET signal is activated again, without any delay,
Power-on Reset
Reset Circuit
SUT[1:0]
Brown-out
Watchdog
Oscillator
Generator
Circuit
Clock
CK
Register (MCUSR)
MCU Status
DATA BUS
Delay Counters
327. The POR is activated whenever
ATmega1284P
TIMEOUT
49
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