ATmega164A Atmel Corporation, ATmega164A Datasheet

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... Power-down Mode: 0.1µA – Power-save Mode: 0.6µA (Including 32kHz RTC) Note: 1. See ”Data Retention” on page 9 ® ® AVR 8-bit Microcontroller (1) for details. 8-bit Atmel Microcontroller with 16/32/64/128K Bytes In-System Programmable Flash ATmega164A ATmega164PA ATmega324A ATmega324PA ATmega644A ATmega644PA ATmega1284 ATmega1284P 8272C–AVR–06/11 ...

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... Pin Configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for Figure 1-1. Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Pinout (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/ICP3/MOSI) PB5 (PCINT14/OC3A/MISO) PB6 (PCINT15/OC3B/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0/T3) PD0 (PCINT25/TXD0) PD1 ...

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... Pinout - DRQFN for ATmega164A/164PA/324A/324PA Figure 1- Table 1- 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P DRQFN - Pinout Top view B1 B15 B2 B14 B3 B13 B4 B12 B5 B11 DRQFN - Pinout PB5 A7 PD3 PB6 B6 PD4 PB7 A8 PD5 RESET B7 PD6 VCC ...

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... Pinout - VFBGA for ATmega164A/164PA/324A/324PA Figure 1- Table 1- 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P VFBGA - Pinout Top view BGA - Pinout GND PB4 PB2 PB6 PB5 PB3 VCC RESET PB7 GND XTAL2 PD0 ...

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... Overview The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instruc- tions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

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... Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful microcon- troller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

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... Comparison Between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P Table 2-1. Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P Device Flash ATmega164A 16 K ATmega164PA 16 K ATmega324A 32 K ATmega324PA 32 K ATmega644A 64 K ATmega644PA 64 K ATmega1284 128 K ATmega1284P 128 K 2 ...

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... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of the JTAG interface, along with special features of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on 2.3.6 Port D (PD7:PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability ...

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... The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 also available for download from the Atmel website. 9 ...

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... The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Block Diagram of the AVR Architecture Program Flash ...

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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...

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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

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... SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P shows the structure of the 32 general purpose working registers in the CPU. AVR CPU General Purpose Working Registers ...

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... The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent, see space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P The X-, Y-, and Z-registers ...

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... SP7 SP6 SP5 R/W R/W R Initial values respectively for the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Stack Pointer size Device ATmega164A/ATmega164PA ATmega324A/ATmega324PA ATmega644A/ATmega644PA ATmega1284/ATmega1284P ( RAMPZ7 RAMPZ6 RAMPZ5 R/W R/W R 15. Note that LPM is not affected by the RAMPZ setting. ...

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... When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P The Parallel Instruction Fetches and Instruction Executions T1 ...

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... SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ...

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... A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incre- mented by three, and the I-bit in SREG is set. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ; set Global Interrupt Enable 18 ...

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... ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an EEPROM Memory for data storage ...

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... SRAM Data Memory Figure 8-2 Memory is organized. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...

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... The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P are all accessible through all these addressing modes. The Register File is described in 13 ...

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... EEPROM Data Memory The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains 512/1K/2K/4Kbytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

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... I/O Memory The I/O space definition of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is shown in All ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...

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... Read/Write Initial Value • Bits 15:12 – Reserved These bits are reserved bits in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and will always read as zero. • Bits 11:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512/1K/2K/4Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511/1023/2047/4096 ...

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... EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P EEPROM Mode Bits Programming EEPM0 ...

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... The calibrated Oscillator is used to time the EEPROM accesses. typical programming time for EEPROM access from the CPU. Table 8-2. Symbol EEPROM write (from CPU) 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 Table 8-2 on page 26 lists the Typ Programming Time 3 ...

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... Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ...

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... Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ...

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... Read/Write Initial Value 8.6.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write Initial Value 8.6.6 GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 MSB R/W R/W R MSB R/W R/W ...

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... Also note that start condition detection in the USI module is carried out asynchro- nously when clk 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P presents the principal clock systems in the AVR and their distribution. All of the clocks 42. The clock systems are detailed below. ...

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... The delay (t Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. ...

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... For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 9-2. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 9-2. The frequency of the Watchdog Oscillator is voltage ”Typical Characteristics” on page Number of Watchdog Oscillator Cycles = 5 ...

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... Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 34. Low Power Crystal Oscillator Operating Modes CKSEL3..1 0.4 - 0.9 100 0.9 - 3.0 3.0 - 8.0 8 the crystal frequency exceeds the specification of the device (depends on V Fuse can be programmed in order to divide the internal frequency by 8 ...

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... Notes: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. ...

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... ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P oscillator is optimized for very low power consumption, and thus when selecting crystals, see ESR recommendations on 9pF and 12 ...

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... Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali- bration value, see the section Table 9-10. Notes: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 9-9. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection Start-up Time from ...

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... When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-13. Table 9-13. Power Conditions BOD enabled Fast rising power Slowly rising power 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 37. Start-up times for the Internal Calibrated RC Oscillator clock selection Start-up Time from Power- down and Power-save Reserved The device is shipped with this option selected ...

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... MCU is kept in Reset during the changes. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to 39 for details. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P External Clock Drive Configuration NC EXTERNAL CLOCK SIGNAL ...

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... Timer/Counter Oscillator ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P uses the same type of crystal oscillator for Low-frequency Crystal Oscillator and Timer/Counter Oscillator. See quency Crystal Oscillator” on page 35 The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a exter- nal clock source. See Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one ...

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... These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchro- nous peripherals is reduced when a division factor is used. The division factors are given in Table 9-16 on page 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

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... Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 9-16. CLKPS3 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Clock Prescaler Select CLKPS2 CLKPS1 0 0 ...

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... To further save power possible to disable the BOD in some sleep modes. See ”BOD Disable(1)” on page 43 10.2 Sleep Modes ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, and their distribution. The figure is helpful in selecting an appropriate sleep mode. their wake up sources and BOD disable ability. Table 10-1. Sleep Mode Idle ...

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... Watchdog interrupt, a Brown-out Reset, a 2-wire serial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT7 pin change interrupt can wakeup the MCU from ADC Noise Reduction mode. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 48. 1. Only available in the ATmega164PA/324PA/644PA/1284P. and clk , while allowing the other clocks to run ...

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... SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ”Clock Sources” on page ”External Interrupts” on page 67 31. ...

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... If the reference is kept on in sleep mode, the output can be used immediately. Refer to age Reference” on page 54 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ”PRR0 – Power Reduction Register 0” on page ”AC - Analog Comparator” on page 240 for details on the start-up time. ...

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... There are three alternative ways to disable the OCD system: • Disable the OCDEN Fuse. • Disable the JTAGEN Fuse. • Write one to the JTD bit in MCUCR. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ”Watchdog Timer” on page 55 for details on how to configure the Watchdog Timer. ) and the ADC clock (clk I/O ADC ” ...

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... To avoid the MCU entering the sleep mode unless it is the programmer’s purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 – ...

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... Bit 4 – PRUSART1: Power Reduction USART1 Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be reinitialized to ensure proper operation. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 (1) ...

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... Bit 7:1 – Reserved • Bit 0 – PRTIM3: Power Reduction Timer/Counter3 Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is enabled, operation will continue like before the shutdown. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 – ...

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... Reset Sources The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...

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... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Power-on Reset Circuit Brown-out Reset Circuit ...

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... Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V delay counter starts the MCU after the Time-out period – t Figure 11-4. External Reset During Operation 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P V POT V CC ...

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... Brown-out Detection ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an On-chip Brown-out Detec- tion (BOD) circuit for monitoring the V level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...

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... Internal Voltage Reference ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an internal bandgap ref- erence. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 11.2.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...

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... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 11.3.2 Overview ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...

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... Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, ~(1< ...

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... Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ...

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... To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 – ...

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... WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con- ditions causing failure, and a safe start-up after the failure. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

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... The different prescaling values and their corresponding time-out periods are shown in Table 11-2 on page . Table 11-2. WDP3 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 60. Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 16K (16384) cycles 1 0 ...

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... ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. For a general explanation of the AVR interrupt handling, refer to 12 ...

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... Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 12-2. BOOTRST Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Reset and Interrupt Vectors (Continued) Program (2) Address Source $0036 ...

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... The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is: Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 ...

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... MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code ; .org 0x1F000 0x1F000 0x1F002 0x1F004 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 1. Applies only to ATmega1284P. r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei < ...

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... The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See the following Code Example. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ... ... jmp SPM_RDY r16,high(RAMEND) ...

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... Assembly Code Example Move_interrupts: C Code Example void Move_interrupts(void) { uchar temp; } 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) ...

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... Read/Write Initial Value • Bits 7:6 – Reserved These bits are reserved in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, and will always read as zero. • Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Interrupt Sense Control Bits The External Interrupts are activated by the external pins INT2:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set ...

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... INT2:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF2:0 flags. See Enable and Sleep Modes” on page 76 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) Interrupt Sense Control ISCn0 ...

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... If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 – ...

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... Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

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... Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

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... Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Functions” on page nate functions. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P and Ground as indicated in CC for a complete list of parameters. Pxn ...

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... To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) Pxn SLEEP ...

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... The maximum and minimum propagation delays are denoted t 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P summarizes the control signals for the pin value. Port Pin Configurations PUD ...

Page 75

... The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P SYSTEM CLK XXX SYNC LATCH ...

Page 76

... External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1< ...

Page 77

... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P or GND is not recommended, since this may cause excessive currents if the pin ...

Page 78

... AVR microcontroller family. Figure 14-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: SLEEP: PTOExn: Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 0 DIEOExn DIEOVxn ...

Page 79

... Refer to the alternate function description for further details. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ...

Page 80

... ADC7:0/PCINT7:0 – Port A, Bit 7:0 ADC7:0, Analog to Digital Converter, Channels 7:0 PCINT7:0, Pin Change Interrupt source 7:0: The PA7:0 pins can serve as external interrupt sources. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Port A Pins Alternate Functions Alternate Function ADC7 (ADC input channel 7) PCINT7 (Pin Change Interrupt 7) ...

Page 81

... DIEOE DIEOV DI AIO Table 14-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P and Table 14-5 on page 81 Figure 14-5 on page Overriding Signals for Alternate Functions in PA7:PA4 PA7/ADC7/ PA6/ADC6/ PCINT7 PCINT6 ...

Page 82

... DDB6. When the pin is forced input, the pull-up can still be controlled by the PORTB6 bit. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Port B Pins Alternate Functions Alternate Functions SCK (SPI Bus Master clock input) ...

Page 83

... INT2, External Interrupt source 2. The PB2 pin can serve as an External Interrupt source to the MCU. PCINT10, Pin Change Interrupt source 10: The PB2 pin can serve as an external interrupt source. • T1/CLKO/PCINT9, Bit 1 T1, Timer/Counter1 counter source. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 83 ...

Page 84

... PVOE PVOV DIEOE DIEOV DI AIO 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P and Table 14-8 relate the alternate functions of Port B to the overriding signals Figure 14-5 on page 78. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the Overriding Signals for Alternate Functions in PB7:PB4 PB7/SCK/ ...

Page 85

... TOSC2, Timer Oscillator pin 2. The PC7 pin can serve as an external interrupt source to the MCU. PCINT23, Pin Change Interrupt source 23: The PC7 pin can serve as an external interrupt source. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Overriding Signals for Alternate Functions in PB3:PB0 PB3/AIN1/OC0B/ PB2/AIN0/INT2/ PCINT11 ...

Page 86

... SCL, 2-wire Serial Bus Clock Line. PCINT16, Pin Change Interrupt source 16: The PC0 pin can serve as an external interrupt source. Table 14-10 shown in 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P and Table 14-11 relate the alternate functions of Port C to the overriding signals Figure 14-5 on page 78. ...

Page 87

... AIO Table 14-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P PC7/TOSC2/ PC6/TOSC1/ PCINT23 PCINT22 AS2 • EXCLK AS2 0 0 AS2 • EXCLK AS2 AS2 • ...

Page 88

... The OC2B pin is also the output pin for the PWM mode timer function. PCINT30, Pin Change Interrupt Source 30: The PD6 pin can serve as an external interrupt source. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Alternate Function OC2A (Timer/Counter2 Output Compare Match A Output) PCINT31 (Pin Change Interrupt 31) ...

Page 89

... RXD0, Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDD0. When the USART forces this pin input, the pull-up can still be controlled by the PORTD0 bit. T3, Timer/Counter3 counter source. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 89 ...

Page 90

... DIEOV DI AIO Table 14-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P and Table 14-14 on page 90 Figure 14-5 on page PD6/ICP1/ PD7/OC2A/ OC2B/ PCINT31 PCINT30 ...

Page 91

... Read/Write Initial Value 14.3.10 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 14.3.11 PINB – Port B Input Pins Address Bit 0x03 (0x23) Read/Write Initial Value 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 (1) (1) JTD BODS BODSE R/W R/W R Only available in the ATmega164PA/324PA/644PA/1284P. ...

Page 92

... Read/Write Initial Value 14.3.16 DDRD – Port D Data Direction Register Bit 0x0A (0x2A) Read/Write Initial Value 14.3.17 PIND – Port D Input Pins Address Bit 0x09 (0x29) Read/Write Initial Value 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 PORTC7 PORTC6 PORTC5 PORTC4 R/W R/W R/W R ...

Page 93

... The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ”Pin Configurations” on page ”Register Description” on page 104 ...

Page 94

... Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P See Section “15.5” on page 95 for details. The Compare Match event will also set the Table 15-1 are also used extensively throughout the document. ...

Page 95

... Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 15-3 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). ...

Page 96

... TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P DATA BUS OCRnx = ...

Page 97

... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P COMnx1 Waveform COMnx0 Generator ...

Page 98

... The timing diagram for the CTC mode is shown in increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 15-2 on page 104, and for phase correct PWM refer to 122). ”Timer/Counter Timing Diagrams” on page 104 ...

Page 99

... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

Page 100

... A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 15-6. The TCNT0 value is in the timing diagram shown as a his- 1 ...

Page 101

... OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 15-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 ...

Page 102

... MAX value in all modes other than phase correct PWM mode. Figure 15-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 15-9 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 15-4 on page f OCnxPCPWM Figure 15-7 Figure 15-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) ...

Page 103

... PWM mode where OCR0A is TOP. Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P I/O Tn /8) I/O MAX - 1 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) ...

Page 104

... Table 15-3 mode. Table 15-3. COM0A1 Note: Table 15-4 on page 105 to phase correct PWM mode. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 COM0A1 COM0A0 COM0B1 R/W R/W R Table 15-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits Compare Output Mode, non-PWM Mode ...

Page 105

... Table 15-6. COM0B1 Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. 1 WGM02 = 1: Toggle OC0A on Compare Match. Clear OC0A on Compare Match when up-counting. Set OC0A on 0 Compare Match when down-counting ...

Page 106

... Note: • Bits 3:2 – Reserved These bits are reserved bits in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- ...

Page 107

... These bits are reserved and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 FOC0A FOC0B – ...

Page 108

... The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Clock Select Bit Description CS01 CS00 ...

Page 109

... OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor- responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 – ...

Page 110

... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 106. Table 15-8, ”Waveform ...

Page 111

... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in enable Timer/Counter1 module. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ”Pin Configurations” on page ”Register Description” on page 132. ”PRR0 – Power Reduction Register 0” on page 48 Figure 16-1 ...

Page 112

... The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener- ator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C). 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Count Clear Control Logic ...

Page 113

... OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 120. The compare match event will also set the Compare Match 240) The Input Capture unit includes a digital filtering unit (Noise Can- Definitions The counter reaches the BOTTOM when it becomes 0x0000 ...

Page 114

... Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ... ; Set TCNTn to 0x01FF ...

Page 115

... TIM16_ReadTCNTn: C Code Example unsigned int TIM16_ReadTCNTn( void ) { } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ...

Page 116

... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and prescaler, see 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ...

Page 117

... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P shows a block diagram of the counter and its surroundings. DATA BUS (8-bit) ...

Page 118

... The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P DATA BUS TEMP (8-bit) ICRnH (8-bit) ...

Page 119

... Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 113. ”Accessing 16-bit Registers” (Figure 16-1 on page 112) ...

Page 120

... The double buffering synchronizes the update of the OCRnx Com- pare Register to either TOP or BOTTOM of the counting sequence. The synchronization 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P shows a block diagram of the Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf ...

Page 121

... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 113. ”Accessing 16-bit Registers” 121 ...

Page 122

... The design of the Output Compare pin logic allows initialization of the OCnx state before the out- put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 132. The COMnx1:0 bits have no effect on the Input Capture unit. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Waveform Generator I/O Figure 16-5 ...

Page 123

... The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the opera- tion of counting external events. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 16-2 on page 132. For fast PWM mode refer to ”Timer/Counter Timing Diagrams” on page ...

Page 124

... TCNTn and OCRnx, and set at BOTTOM. In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor- 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 when OCRnA is set to zero (0x0000) ...

Page 125

... OCRnx Registers are written. The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P log R = ...

Page 126

... TCNTn and OCRnx while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 OCnxPWM = f /2 when OCRnA is set to zero (0x0000) ...

Page 127

... Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P log = ---------------------------------- - ...

Page 128

... Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P f OCnxPCPWM 16-9). Figure 16-8 illustrates, changing the Table on page ...

Page 129

... Figure 16-9 cal in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 PFCPWM Figure 16-9. The figure shows phase and frequency correct ...

Page 130

... The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 16-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling Figure 16-11 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P f OCnxPFCPWM Figure 16-10 clk I/O ...

Page 131

... TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. Figure 16-12. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) (PC and PFC PWM) and ICFn Figure 16-13 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P clk I/O clk Tn (clk /8) I/O ...

Page 132

... When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen- dent of the WGMn3:0 bits setting. when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM). Table 16-2. COMnA1/COMnB1 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P clk I/O clk Tn (clk ...

Page 133

... Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to Compare Output Mode, Fast PWM ...

Page 134

... When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) WGMn0 Timer/Counter Mode of ...

Page 135

... The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-11. Clock Select Bit Description ...

Page 136

... Writing to the TCNT3 Register blocks (removes) the compare match on the following timer clock for all compare units. 16.11.6 OCR1AH and OCR1AL – Output Compare Register1 A Bit (0x89) (0x88) Read/Write Initial Value 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 TCNT1[15:8] TCNT1[7:0] R/W R/W R/W ...

Page 137

... TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

Page 138

... When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1A Flag, located in TIFR1, is set. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

Page 139

... TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and will always read as zero. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 55) is executed when the TOV1 Flag, located in TIFR1, is set – – ...

Page 140

... WGMn3 used as the TOP value, the ICF3 Flag is set when the coun- ter reaches the TOP value. ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF3 can be cleared by writing a logic one to its bit location. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 – ...

Page 141

... Flag behavior when using another WGMn3:0 bit setting. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit location. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 16-5 on page 134 for the TOV3 141 ...

Page 142

... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The Power Reduction Timer/Counter2 bit, PRTIM2, in page 48 Figure 17-1. 8-bit Timer/Counter Block Diagram 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ”Pin Configurations” on page ”Register Description” on page must be written to zero to enable Timer/Counter2 module. Count Clear ...

Page 143

... ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see – Asynchronous Status Register” on page ”Timer/Counter Prescaler” on page 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 Table 17-1 are also used extensively throughout the section. ...

Page 144

... Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe- cuted. Alternatively, the Output Compare Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P DATA BUS count clear ...

Page 145

... This feature allows OCR2x to be initial- ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P shows a block diagram of the Output Compare unit. DATA BUS OCRnx ...

Page 146

... The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Waveform Generator clk ...

Page 147

... OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ”Register Description” on page 156. Table 17-5 on page 157 ...

Page 148

... BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

Page 149

... MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits.) 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 17-6 on page 149. The TCNT2 value is in the timing diagram 1 ...

Page 150

... The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 17-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating when OCR2A is set to zero ...

Page 151

... Figure 17-8 on page 152 shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P f OCnxPCPWM Figure 17-7 on page 150 Figure 17-7 on page contains timing data for basic Timer/Counter operation. The figure Table 17-4 on page 157) ...

Page 152

... TCNTn TOVn Figure 17-10 on page 152 Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f (clk TCNTn OCRnx OCFnx 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF2A in all modes except CTC mode ...

Page 153

... Output Compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f ...

Page 154

... Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ) again becomes active, TCNT2 will read as the previous value (before entering sleep) 154 ...

Page 155

... For Timer/Counter2, the possible prescaled selections are: clk clk /128, clk T2S Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P clk clk I/O T2S Clear TOSC1 AS2 ...

Page 156

... CTC mode (non-PWM). Table 17-2. COM2A1 Table 17-3 mode. Table 17-3. COM2A1 Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 COM2A1 COM2A0 COM2B1 R/W R/W R Table 17-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits Compare Output Mode, non-PWM Mode COM2A0 ...

Page 157

... Table 17-6. COM2B1 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM2A0 Description 0 Normal port operation, OC2A disconnected. WGM22 = 0: Normal Port Operation, OC2A Disconnected. ...

Page 158

... Notes: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See page 148 for more details. shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor- ...

Page 159

... Bit 3 – WGM22: Waveform Generation Mode See the description in the • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 17-9 on page 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 FOC2A FOC2B – ...

Page 160

... The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2B pin. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Clock Select Bit Description CS21 CS20 ...

Page 161

... A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 – ...

Page 162

... Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 – ...

Page 163

... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except ifthe TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 TSM – ...

Page 164

... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and peripheral devices or between several AVR devices. USART can also be used in Master SPI mode, see The Power Reduction SPI bit, PRSPI written to zero to enable SPI module. ...

Page 165

... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 18-2. The sys- SHIFT ENABLE ...

Page 166

... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Table 18-1. For more details on automatic port overrides, refer to 78. ...

Page 167

... C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) ...

Page 168

... Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) SPCR,r17 out ret ; Wait for reception complete ...

Page 169

... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 18-2 on page 170 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P and Figure 18-4 on page 170. Data bits are shifted out and latched in on Table 18-3 on page 171 ...

Page 170

... Table 18-2. SPI Mode Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P SPI Modes Conditions 0 CPOL=0, CPHA=0 1 CPOL=0, CPHA=1 2 CPOL=1, CPHA=0 3 CPOL=1, CPHA=1 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO ...

Page 171

... Table 18-3. • Bit 2 – CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to functionality is summarized below: Table 18-4. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 SPIE SPE DORD ...

Page 172

... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is also used for program memory and EEPROM downloading or uploading. See gramming and verification. 8272C–AVR–06/11 ...

Page 173

... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

Page 174

... Double Speed Asynchronous Communication Mode 19.2 USART1 and USART0 The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has two USART’s, USART0 and USART1. The functionality for all USART’s is described below, most register and bit references in this sec- tion are written in general form. A lower case “n” replaces the USART number. ...

Page 175

... Master synchronous and Slave synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) UBRR[H:L] BAUD RATE GENERATOR ...

Page 176

... UMSELn, U2Xn and DDR_XCKn bits. Table 19-1 on page 177 for calculating the UBRRn value for each mode of operation using an internally generated clock source. Note: BAUD 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P shows a block diagram of the clock generation logic. UBRR fosc UBRR+1 Prescaling Down-Counter ...

Page 177

... The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process intro- 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud ...

Page 178

... When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 19-4 on page 179 brackets are optional. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P depends on the stability of the system clock source therefore recommended to osc UCPOL = 1 XCK ...

Page 179

... Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXCn Flag can be used to check that the Transmitter has completed all transfers, and the RXC Flag can be used to 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (IDLE ...

Page 180

... USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If syn- chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Set baud rate out UBRRnH, r17 ...

Page 181

... UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ...

Page 182

... When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1)(2) ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ...

Page 183

... Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 183 ...

Page 184

... FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ...

Page 185

... The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ...

Page 186

... Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ”Parity Bit Calculation” on page 179 and ” ...

Page 187

... Normal mode, and eight times the baud rate for Double Speed mode. The hor- izontal arrows illustrate the synchronization variation due to the sampling process. Note the 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P (1) sbis UCSRnA, RXCn ret ...

Page 188

... Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 19-7 on page 189 of the start bit of the next frame. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P RxD IDLE 0 0 ...

Page 189

... The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate slow Table 19-2 on page 190 that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P RxD Sample (U2X = Sample (U2X = Figure 19-7 on page 189 ...

Page 190

... If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) ...

Page 191

... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 191 ...

Page 192

... Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 ...

Page 193

... Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P ”Multi-processor Communication Mode” on page 7 6 ...

Page 194

... UCSRnC – USART Control and Status Register n C Bit Read/Write Initial Value • Bits 7:6 – UMSELn1:0 USART Mode Select These bits select the mode of operation of the USARTn as shown in Table 19-4. UMSELn1 Note: 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 UMSELn1 UMSELn0 UPMn1 R/W R/W R/W ...

Page 195

... Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe frame the Receiver and Transmitter use. Table 19-7. UCSZn2 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P UPMn Bits Settings UPMn1 UPMn0 0 0 ...

Page 196

... UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P UCPOLn Bit Settings Transmitted Data Changed (Output of TxDn Pin) ...

Page 197

... Max. 62.5kbps 1. UBRR = 0, Error = 0.0% 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 189). The error values are calculated using the following equation: BaudRate ⎛ Error[%] = ------------------------------------------------------- - 1 ⎝ 1.8432MHz osc U2Xn = 0 Error UBRR Error UBRR ...

Page 198

... Max. 230.4kbps 460.8kbps 1. UBRR = 0, Error = 0.0% 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 4.0000MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0.0% 16 2.1% 34 0.0% 12 0.2% 25 0.0% 8 -3. ...

Page 199

... Max. 0.5Mbps 1. UBRR = 0, Error = 0.0% 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284/P 11.0592 f = osc U2Xn = 0 Error UBRR Error UBRR -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – ...

Page 200

... Max. 1Mbps 1. UBRR = 0, Error = 0.0% 8272C–AVR–06/11 ATmega164A/PA/324A/PA/644A/PA/1284 18.4320MHz osc U2Xn = 0 Error UBRR Error UBRR 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – ...