ATmega164P Automotive Atmel Corporation, ATmega164P Automotive Datasheet - Page 75

• Manufacturer Part Number: ATmega164P Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega164P Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.5.1
13.5.2
7701E–AVR–02/11
Force Output Compare
Compare Match Blocking by TCNT0 Write
Figure 13-3. Output Compare Unit, Block Diagram
The OCR0x registers are double buffered when using any of the pulse width modulation
(PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR0x
compare registers to either top or bottom of the counting sequence. The synchronization pre-
vents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR0x register access may seem complex, but this is not the case. When the double
buffering is enabled, the CPU has access to the OCR0x buffer register, and if double buffering
is disabled the CPU will access the OCR0x directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced
by writing a logical one to the force output compare (0x) bit. Forcing compare match will not
set the OCF0x flag or reload/clear the timer, but the OC0x pin will be updated as if a real com-
pare match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set,
cleared, or toggled).
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in
the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be
initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter
clock is enabled.
bottom
FOCn
top
OCRnx
Atmel ATtiny24/44/84 [Preliminary]
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMnX1:0
TCNTn
OCFnx (Int.Req.)
OCnx
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