ATmega165P Atmel Corporation, ATmega165P Datasheet - Page 280

• Manufacturer Part Number: ATmega165P
• Manufacturer: Atmel Corporation

Specifications of ATmega165P

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.8.2
8019K–AVR–11/10
Serial Programming Algorithm
When writing serial data to the ATmega165P, data is clocked on the rising edge of SCK.
When reading data from the ATmega165P, data is clocked on the falling edge of SCK. See
ure 25-8 on page 281
To program and verify the ATmega165P in the serial programming mode, the following
sequence is recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of synchro-
4. The Flash is programmed one page at a time. The page size is found in
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the con-
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
page
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for a given address. The Program Memory Page is stored by loading the Write
Program Memory Page instruction with the 7 MSB of the address. If polling
not used, the user must wait at least t
25-14 on page
operation completes can result in incorrect programming.
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling
user must wait at least t
281). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 4 MSB of the address. When using
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page
instruction is altered. The remaining locations remain unchanged. If polling (
not used, the user must wait at least t
25-14 on page
programmed.
tent at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
269. The memory page is loaded one byte at a time by supplying the 6 LSB of the
CC
power off.
281). Accessing the serial programming interface before the Flash write
281). In a chip erased device, no 0xFF in the data file(s) need to be
for timing details.
WD_EEPROM
CC
and GND while RESET and SCK are set to “0”. In some sys-
before issuing the next byte (see
WD_EEPROM
WD_FLASH
before issuing the next page (see
before issuing the next page (see
(
RDY/BSY) is not used, the
Table 25-15 on page
ATmega165P
Table 25-14 on page
Table 25-7 on
(
RDY/BSY) is
RDY/BSY
Table
282):
Table
) is
Fig-
280