ATmega168 Automotive Atmel Corporation, ATmega168 Automotive Datasheet - Page 72

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ATmega168 Automotive

Manufacturer Part Number
ATmega168 Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATmega168 Automotive

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
13. 8-bit Timer/Counter0 with PWM
13.1
13.2
13.2.1
72
Features
Overview
Atmel ATtiny24/44/84 [Preliminary]
Registers
Timer/counter 0 is a general purpose 8-bit timer/counter module, with two independent out-
put compare units, and with PWM support. It allows accurate program execution timing (event
management) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in
the actual placement of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the
Figure 13-1. 8-bit Timer/Counter Block Diagram
The timer/counter (TCNT0) and output compare registers (OCR0A and OCR0B) are 8-bit reg-
isters. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
timer/counter 0 interrupt flag register (TIFR0). All interrupts are individually masked with the
timer interrupt mask register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source
on the T0 pin. The Clock Select logic block controls which clock source and edge the
Two Independent Output Compare Units
Double Buffered Output Compare Registers
Clear Timer on Compare Match (Auto Reload)
Glitch Free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
Timer/Counter
“Register Description” on page
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
Direction
Count
Clear
Control Logic
Figure 1-1 on page
TOP
=
TCCRnB
Value
BOTTOM
Fixed
TOP
clk
=
Tn
0
84.
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
Generation
Generation
2. CPU accessible I/O Registers,
( From Prescaler )
Waveform
Waveform
Detector
Edge
Figure 13-1 on page
OCnA
OCnB
Tn
7701E–AVR–02/11
72. For

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