ATmega168P

Manufacturer Part NumberATmega168P
ManufacturerAtmel Corporation
ATmega168P datasheets
 

Specifications of ATmega168P

Flash (kbytes)16 KbytesPin Count32
Max. Operating Frequency20 MHzCpu8-bit AVR
# Of Touch Channels16Hardware Qtouch AcquisitionNo
Max I/o Pins23Ext Interrupts24
Usb SpeedNoUsb InterfaceNo
Spi2Twi (i2c)1
Uart1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels8Adc Resolution (bits)10
Adc Speed (ksps)15Analog Comparators1
Resistive Touch ScreenNoTemp. SensorYes
Crypto EngineNoSram (kbytes)1
Eeprom (bytes)512Self Program MemoryYES
Dram MemoryNoNand InterfaceNo
PicopowerYesTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers3Output Compare Channels6
Input Capture Channels1Pwm Channels6
32khz RtcYesCalibrated Rc OscillatorYes
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Page 304/420

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28.7.14
Reading the Calibration Byte
The algorithm for reading the Calibration byte is as follows (refer to
page 298
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
28.7.15
Parallel Programming Characteristics
For chracteristics of the Parallel Programming, see
page
320.
28.8
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
Figure 28-7. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
ATmega48P/88P/168P
304
for details on Command and Address loading):
MOSI
MISO
SCK
XTAL1
RESET
GND
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
AV
2. V
- 0.3V <
< V
+ 0.3V, however,
CC
CC
CC
< 12 MHz, 3 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
”Programming the Flash” on
”Parallel Programming Characteristics” on
Table 28-15 on page
(1)
+1.8 - 5.5V
VCC
(2)
+1.8 - 5.5V
AVCC
AV
should always be within 1.8 - 5.5V
CC
>= 12 MHz
ck
>= 12 MHz
ck
305, the pin
8025M–AVR–6/11