ATmega3250P Atmel Corporation, ATmega3250P Datasheet

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ATmega3250P

Manufacturer Part Number
ATmega3250P
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega3250P

Flash (kbytes)
32 Kbytes
Pin Count
100
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
25
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Features
High Performance, Low Power AVR
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Speed Grade:
Temperature range:
Ultra-Low Power Consumption
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-Chip 2-cycle Multiplier
– 32K Bytes of In-System Self-programmable Flash program memory
– 1K Bytes EEPROM
– 2K Bytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
– 54/69 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP
– ATmega325PV/ATmega3250PV:
– ATmega325P/3250P:
– -40°C to 85°C Industrial
– Active Mode:
– Power-down Mode:
– Power-save Mode:
Mode
Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
420 µA at 1 MHz, 1.8V
40 nA at 1.8V
750 nA at 1.8V
®
8-Bit Microcontroller
(1)
8-bit
Microcontroller
with 32K Bytes
In-System
Programmable
Flash
ATmega325P/V
ATmega3250P/V
Preliminary
8023FS–AVR–07/09

Related parts for ATmega3250P

ATmega3250P Summary of contents

Page 1

... Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and Packages – 54/69 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP • Speed Grade: – ATmega325PV/ATmega3250PV MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega325P/3250P MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...

Page 2

... Pin Configurations Figure 1-1. ATmega325P/3250P 2 Pinout ATmega3250P DNC 1 2 (RXD/PCINT0) PE0 INDEX CORNER (TXD/PCINT1) PE1 3 4 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 5 6 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 7 8 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 9 10 VCC GND 11 12 DNC (PCINT24) PJ0 13 14 (PCINT25) PJ1 DNC 15 16 ...

Page 3

Figure 1-2. Note: 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. ...

Page 4

Block Diagram Figure 2-1. Block Diagram GND VCC DATA REGISTER PORTF AVCC AGND AREF JTAG TAP ON-CHIP DEBUG BOUNDARY- SCAN PROGRAMMING LOGIC USART DATA REGISTER PORTE The AVR core combines a rich instruction set with 32 general purpose working ...

Page 5

... The ATmega325P/3250P AVR is supported with a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison between ATmega325P and ATmega3250P The ATmega325P and ATmega3250P differs only in memory sizes, pin count and pinout. 2-1 on page 5 Table 2-1. Device ATmega325P ATmega3250P 8023FS– ...

Page 6

Pin Descriptions The following section describes the I/O-pin special functions. 2.3 Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ...

Page 7

... As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3250P as listed on page 75. ...

Page 8

RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Characterizations” on page 2.3.13 XTAL1 ...

Page 9

Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 8023FS–AVR–07/09 ATmega325P/3250P 9 ...

Page 10

Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code ...

Page 11

... Reserved - (0xCC) Reserved - (0xCB) Reserved - (0xCA) Reserved - (0xC9) Reserved - (0xC8) Reserved - (0xC7) UDR0 (0xC6) UBRR0H (0xC5) 8023FS–AVR–07/09 Registers with bold type only available in ATmega3250P. Bit 6 Bit 5 Bit ...

Page 12

Address Name Bit 7 UBRR0L (0xC4) Reserved - (0xC3) UCSR0C - (0xC2) UCSR0B RXCIE0 (0xC1) UCSR0A RXC0 (0xC0) Reserved - (0xBF) Reserved - (0xBE) Reserved - (0xBD) Reserved - (0xBC) Reserved - (0xBB) USIDR (0xBA) USISR USISIF (0xB9) USICR USISIE ...

Page 13

Address Name Bit 7 TCNT1H (0x85) TCNT1L (0x84) Reserved - (0x83) TCCR1C FOC1A (0x82) TCCR1B ICNC1 (0x81) TCCR1A COM1A1 (0x80) DIDR1 - (0x7F) DIDR0 ADC7D (0x7E) Reserved - (0x7D) ADMUX REFS1 (0x7C) ADCSRB - (0x7B) ADCSRA ADEN (0x7A) ADCH (0x79) ...

Page 14

Address Name Bit 7 TCNT0 0x26 (0x46) Reserved - 0x25 (0x45) TCCR0A FOC0A 0x24 (0x44) GTCCR TSM 0x23 (0x43) EEARH - 0x22 (0x42) EEARL 0x21 (0x41) EEDR 0x20 (0x40) EECR - 0x1F (0x3F) GPIOR0 0x1E (0x3E) EIMSK PCIE3 0x1D (0x3D) ...

Page 15

Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

Page 16

Mnemonics Operands BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register ...

Page 17

Mnemonics Operands PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 8023FS–AVR–07/09 Description STACK ← ← STACK (see specific descr. for Sleep ...

Page 18

Ordering Information 30.1 ATmega325P (3) Speed (MHz) Power Supply 10 1.8 - 5.5V 20 2.7 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information ...

Page 19

... Figure 26-1 on page 306 CC 100A 100-lead 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 8023FS–AVR–07/09 (2) Ordering Code Package Type ATmega3250PV-10AU ATmega3250P-20AU and Figure 26-2 on page 306. Package Type ATmega325P/3250P (1) Operational Range Industrial 100A 0⋅C to 85⋅C) ...

Page 20

Packaging Information 31.1 64A PIN 0°~7° L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...

Page 21

Marked Pin TOP VIEW BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R ...

Page 22

PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...

Page 23

Errata 32.1 ATmega325P rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer. • Using BOD disable will make the chip reset. 1. Interrupts may be lost when writing the timer registers in ...

Page 24

... Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 32.6 ATmega3250P rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. ...

Page 25

... Updated DEVICE and JTAG ID in Updated ”System and Reset Characterizations” on page Updated ”Typical Characteristics” on page 314 Initial version. ATmega325P/3250P 15. 32. ”External Interrupts” on page 85. 308. and ”ATmega3250P rev. C” on 274. Table 25-6 on page 274 308. 58. 147. 356 ...

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