ATmega329 Atmel Corporation, ATmega329 Datasheet
ATmega329
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Page 1
... Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – Segment LCD Driver (ATmega329/ATmega649) – Segment LCD Driver (ATmega3290/ATmega6490) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – ...
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... Pin Configurations Figure 1-1. Pinout ATmega3290/6490 1 LCDCAP 2 (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 5 (AIN1/PCINT3) PE3 6 (USCK/SCL/PCINT4) PE4 7 (DI/SDA/PCINT5) PE5 8 (DO/PCINT6) PE6 9 (CLKO/PCINT7) PE7 VCC 10 GND 11 12 DNC 13 (PCINT24/SEG35) PJ0 14 (PCINT25/SEG34) PJ1 15 DNC 16 DNC 17 DNC DNC 18 19 (SS/PCINT8) PB0 20 (SCK/PCINT9) PB1 21 (MOSI/PCINT10) PB2 ...
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... Figure 1-2. Pinout ATmega329/649 LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 14 (OC1A/PCINT13) PB5 15 (OC1B/PCINT14) PB6 16 Note: 2552K–AVR–04/11 INDEX CORNER ATmega329/649 The large center pad underneath the QFN/MLF packages is made of metal and internally con- nected to GND ...
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... Overview The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architec- ture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a pow- erful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The Atmel ATmega329/3290/649/6490 is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...
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... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on 2.3.4 Port B (PB7 ...
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... As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listed on page 2 ...
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... As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3290/6490 as listed on page 75. ...
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... I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 2552K–AVR–04/11 but increases the time until V LCD 1. ATmega329/3290/649/6490 ). A large capacitance reduces LCD reaches its target value. LCD Fig- ...
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... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. ATmega329/3290/649/6490 10 Block Diagram of the AVR Architecture ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega329/3290/649/6490 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATmega329/3290/649/6490 ...
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... Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a data memory address, mapping them ATmega329/3290/649/6490 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value ATmega329/3290/649/6490 14 The X-, Y-, and Z-registers R27 (0x1B) 15 ...
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... Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back for details. ATmega329/3290/649/6490 “Memory Program- “Interrupts” on page T4 T4 49. The list also ...
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... SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ ATmega329/3290/649/6490 16 “Boot Loader Support – Read-While-Write Self-Programming” on page ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 2552K–AVR–04/11 ATmega329/3290/649/6490 ; set Global Interrupt Enable 17 ...
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... This section describes the different memories in the ATmega329/3290/649/6490. The Atmel ® AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega329/3290/649/6490 features an EEPROM Memory for data stor- age. All three memory spaces are linear. 7.1 In-System Reprogrammable Flash Program Memory The ATmega329/3290/649/6490 contains 32/64Kbytes On-chip In-System Reprogrammable Flash memory for program storage ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2,048 bytes of internal data SRAM in the ATmega329/3290/649/6490 are all accessible through all these addressing modes. The Register File is described in ter File” on page Figure 7-2 ...
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... Figure 7-3. 7.3 EEPROM Data Memory The ATmega329/3290/649/6490 contains 1/2K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... The I/O space definition of the ATmega329/3290/649/6490 is shown in page 365. All ATmega329/3290/649/6490 I/Os and peripherals are placed in the I/O space. All I/O loca- tions may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions ...
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... Read/Write Initial Value • Bits 15:11 – Reserved Bits These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero. • Bits 10:0 – EEAR10:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1/2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023/2047 ...
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... EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. Table 7-1. Symbol EEPROM write (from CPU) 2552K–AVR–04/11 ATmega329/3290/649/6490 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 27,072 “Boot Loader for details about Boot ...
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... EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. ATmega329/3290/649/6490 24 ; 2552K–AVR–04/11 ...
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... EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR MSB R/W R/W R/W R MSB R/W R/W R/W R MSB R/W R/W R/W R ATmega329/3290/649/6490 LSB R/W R/W R/W R LSB R/W R/W R/W R LSB R/W R/W R/W R GPIOR2 GPIOR1 ...
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... Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. ATmega329/3290/649/6490 26 presents the principal clock systems in the AVR and their distribution. All of the clocks 35. The clock systems are detailed below. ...
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... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 335. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out (V CC 4.1ms 65ms ATmega329/3290/649/6490 (1) CKSEL3..0 1111 - 1000 0111 - 0110 0010 0000 0011, 0001, 0101, 0100 = 3.0V) Number of Cycles CC 4 ...
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... The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-3. CKSEL3..1 Notes: The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 8-4. Table 8-4. CKSEL0 ATmega329/3290/649/6490 28 Table 8-3. For ceramic resonators, the capacitor values given by Crystal Oscillator Connections C2 C1 Crystal Oscillator Operating Modes Frequency Range (MHz) (1) 100 0 ...
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... Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save ( 32K CK 1. This option should only be used if frequency stability at start-up is not important for the application for more details. ATmega329/3290/649/6490 Additional Delay from Reset Recommended (V = 5.0V) Usage CC 14CK + 4.1ms ...
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... When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-8 on page Table 8-8. Power Conditions BOD enabled Fast rising power Slowly rising power Note: ATmega329/3290/649/6490 30 30. If selected, it will operate with no external components. During reset, Table 28-2 on page 329. “Calibration Byte” on page Internal Calibrated RC Oscillator Operating Modes (2) ...
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... The clock will be out- put also during reset and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including internal RC Oscillator, can be selected when CLKO 2552K–AVR–04/11 ATmega329/3290/649/6490 External Clock Drive Configuration NC EXTERNAL ...
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... System Clock Prescaler The ATmega329/3290/649/6490 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the require- ment for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. 2552K–AVR–04/11 ATmega329/3290/649/6490 ...
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... Table 8-11. CLKPS3 ATmega329/3290/649/6490 34 Clock Prescaler Select CLKPS2 CLKPS1 CLKPS0 Clock Division Factor ...
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... Only recommended with external crystal or resonator selected as clock source either LCD controller or Timer/Counter2 is running in asynchronous mode. 3. For INT0, only level interrupt 2552K–AVR–04/11 for a summary enabled interrupt occurs while the MCU presents the different clock systems in the ATmega329/3290/649/6490, Oscillators ( ...
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... Reset Time-out period, as described in 9.4 Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: ATmega329/3290/649/6490 36 and clk , while allowing the other clocks to run. CPU FLASH ...
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... When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, 2552K–AVR–04/11 ATmega329/3290/649/6490 “PRR – Power Reduction Register” on page “Analog to Digital Converter” on page 211 ...
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... There are three alternative ways to avoid this: • Disable OCDEN Fuse. • Disable JTAGEN Fuse. ATmega329/3290/649/6490 38 “Analog Comparator” on page 207 for details on the start-up time. “Watchdog Timer” on page 45 for details on how to configure the Watchdog Timer. ...
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... Sleep Mode Select SM1 SM0 Standby mode is only recommended for use with external crystals or resonators. ATmega329/3290/649/6490 SM2 SM1 SM0 SE R/W R/W R/W R Table 9-2. Sleep Mode Idle ADC Noise Reduction Power-down Power-save ...
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... Read/Write Initial Value • Bits Reserved bits These bits are reserved bits in ATmega329/3290/649/6490 and will always read as zero. • Bit 4 - PRLCD: Power Reduction LCD Writing logic one to this bit shuts down the LCD controller. The LCD controller must be disabled and the display discharged before shut down. See "Disabling the LCD" on page 217 for details on how to disable the LCD controller. • ...
Page 41
... SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in 10.2 Reset Sources The ATmega329/3290/649/6490 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
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... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V CC Figure 10-2. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL ATmega329/3290/649/6490 42 Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor SPIKE ...
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... MCU after the Time-out period – t Figure 10-4. External Reset During Operation 10.5 Brown-out Detection ATmega329/3290/649/6490 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V CC BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as ...
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... Figure 10-6. Watchdog Reset During Operation 10.7 Internal Voltage Reference ATmega329/3290/649/6490 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega329/3290/649/6490 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to ...
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... WDTCR, r16 ret C Code Example void WDT_off(void Reset WDT */ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } Note: ATmega329/3290/649/6490 46 Watchdog Timer Prescale Select Number of WDT WDP1 WDP0 Oscillator Cycles 0 0 16K cycles 0 1 32K cycles ...
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... This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. 2552K–AVR–04/11 ATmega329/3290/649/6490 – ...
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... Initial Value • Bits 7:5 – Reserved Bits These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... ATmega329/3290/649/6490. For a general explanation of the AVR interrupt handling, refer to “ ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega329/3290/649/6490 is: Addre ss 0x000 0 0x000 2 0x000 4 0x000 ...
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... When the BOOTRST Fuse is programmed and the Boot section size set to 4K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code .org 0x0002 0x0002 2552K–AVR–04/11 ATmega329/3290/649/6490 jmp USI_OVF jmp ANA_COMP jmp ...
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... When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter- mined by the BOOTSZ Fuses. Refer to the section ATmega329/3290/649/6490 52 jmp PCINT0 ...
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... MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) out MCUCR, r17 ret /* Enable change of Interrupt Vectors */ MCUCR |= (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR |= (1<<IVSEL); ATmega329/3290/649/6490 “Boot Loader Support – Read-While- for details on Boot Lock bits. 53 ...
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... The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 12.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 12-1. Pin Change Interrupt ATmega329/3290/649/6490 54 “Clock Systems and their Distribution” on page 26. pin_lat PCINT(0) D ...
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... The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT3 Interrupt Vector. PCINT30..24 pins are enabled individually by the PCMSK3 Register. This bit is reserved bit in ATmega329/649 and should always be written to zero. • Bit 6 – PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled ...
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... Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. This bit is reserved bit in ATmega329/649 and will always be read as zero. • Bit 6 – PCIF2: Pin Change Interrupt Flag 2 When a logic change on any PCINT24..16 pin triggers an interrupt request, PCIF2 becomes set (one) ...
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... PCINT30 PCINT29 PCINT28 R R/W R PCINT23 PCINT22 PCINT21 PCINT20 R/W R/W R/W R PCMSK3 and PCMSK2 are only present in ATmega3290/6490. ATmega329/3290/649/6490 PCINT27 PCINT26 PCINT25 PCINT24 R/W R/W R/W R PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R PCMSK3 ...
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... Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATmega329/3290/649/6490 ...
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... Using the I/O port as General Digital I/O is described in 60. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 13-1. Refer to Pxn C pin “ ...
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... If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to ATmega329/3290/649/6490 60 65. Refer to the individual module sections for a full description of the alter- ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 13-2, the PINxn Register bit and the preceding latch con- pd,max ATmega329/3290/649/6490 Pull-up Comment No Tri-state (Hi-Z) Pxn will source current if ext. pulled Yes low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 13-3 shows a timing dia- and t respectively ...
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... Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS ATmega329/3290/649/6490 62 SYSTEM CLK XXX SYNC LATCH PINxn r17 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF 2552K–AVR–04/11 ...
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... Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega329/3290/649/6490 0xFF nop in r17, PINx 0x00 t pd 0xFF 63 ...
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... Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ATmega329/3290/649/6490 64 (1) r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) ...
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... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega329/3290/649/6490 Figure 13-2 can be overridden by PUD ...
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... Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog This is the Analog Input/output to/from alternate Input/Output functions. The signal is connected directly to the pad, and can be used bi-directionally. “Pinout ATmega3290/6490” on page 2 for details. Fig- and “Pinout 2552K–AVR–04/11 ...
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... Overriding Signals for Alternate Functions in PA7..PA4 PA7/SEG3 PA6/SEG2 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – LCDSEG LCDSEG ATmega329/3290/649/6490 PA5/SEG1 PA4/SEG0 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – LCDSEG LCDSEG ...
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... OC2, Output Compare Match A output: The PB7 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function. ATmega329/3290/649/6490 68 Overriding Signals for Alternate Functions in PA3..PA0 ...
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... DDB1. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB1. When the pin is forced input, the pull-up can still be controlled by the PORTB1 bit. PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt source. 2552K–AVR–04/11 ATmega329/3290/649/6490 69 ...
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... PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega329/3290/649/6490 70 and Table 13-8 relate the alternate functions of Port B to the overriding signals Figure 13-5 on page 65. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the Overriding Signals for Alternate Functions in PB7:PB4 PB7/OC2A/ PB6/OC1B/ PCINT15 ...
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... SEG (LCD Front Plane14/10) SEG (LCD Front Plane 15/11) SEG (LCD Front Plane 16/12) and Table 13-11 relate the alternate functions of Port C to the overriding signals Figure 13-5 on page 65. ATmega329/3290/649/6490 PB1/SCK/ PB0/SS/ PCINT9 PCINT8 SPE • MSTR SPE • MSTR PORTB1 • PUD PORTB0 • PUD SPE • ...
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... DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega329/3290/649/6490 72 PC7/SEG5 PC6/SEG6 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – ...
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... SEG (LCD front plane 22/18) SEG (LCD front plane 23/19) SEG (LCD front plane 24/20) INT0/SEG (External Interrupt0 Input or LCD front plane 25/21) ICP1/SEG (Timer/Counter1 Input Capture pin or LCD front plane 26/22) and Table 13-14 relates the alternate functions of Port D to the overriding signals Figure 13-5 on page 65. ATmega329/3290/649/6490 Table 13-12. 73 ...
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... PTOE DIEOE DIEOV DI AIO Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega329/3290/649/6490 74 PD7/SEG(19/15) PD6/SEG(20/16) LCDEN • LCDEN • (LCDPM) (LCDPM LCDEN • LCDEN • (LCDPM) (LCDPM – ...
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... AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. PCINT3, Pin Change Interrupt Source 3: The PE3 pin can serve as an external interrupt source. 2552K–AVR–04/11 ATmega329/3290/649/6490 Alternate Function PCINT7 (Pin Change Interrupt7) CLKO (Divided System Clock) ...
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... Table 13-16. Overriding Signals for Alternate Functions PE7:PE4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: ATmega329/3290/649/6490 76 and Table 13-17 relates the alternate functions of Port E to the overriding signals Figure 13-5 on page 65. PE6/DO/ PE7/PCINT7 PCINT6 (1) CKOUT ...
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... ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) ATmega329/3290/649/6490 PE1/TXD/ PE0/RXD/PCINT PCINT1 0 TXEN RXEN 0 PORTE0 • ...
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... I/O pin. • ADC3 - ADC0 – Port F, Bit 3:0 Analog to Digital Converter, Channel 3-0. Table 13-19. Overriding Signals for Alternate Functions in PF7:PF4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega329/3290/649/6490 PF7/ADC7/TDI PF6/ADC6/TDO JTAGEN JTAGEN 1 1 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 ...
Page 79
... T0/SEG (Timer/Counter0 Clock Input or LCD Front Plane 32/23) T1/SEG (Timer/Counter1 Clock Input or LCD Front Plane 33/24) SEG (LCD Front Plane 4/4) SEG (LCD Front Plane 17/13) SEG (LCD Front Plane 18/14) 1. Port G, PG5 is input only. Pull-up is always on. See Table 27-3 on page 294 for RSTDISBL fuse. ATmega329/3290/649/6490 PF1/ADC1 PF0/ADC0 ...
Page 80
... Table 13-21 shown in Table 13-22. Overriding Signals for Alternate Functions in PG4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega329/3290/649/6490 80 and Table 13-22 relates the alternate functions of Port G to the overriding signals Figure 13-5 on page 65. PG4/T0/ SEG(32/23) LCDEN 0 LCDEN – ...
Page 81
... DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.8 Alternate Functions of Port H Port H is only present in ATmega3290/6490. The alternate pin configuration is as follows: Table 13-24. Port H Pins Alternate Functions Port Pin PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 The alternate pin configuration is as follows: • ...
Page 82
... PCINT19, Pin Change Interrupt Source 19: The PH3 pin can serve as an external interrupt source. SEG, LCD front plane 7. • PCINT18/SEG – Port H, Bit 2 PCINT18, Pin Change Interrupt Source 18: The PH2 pin can serve as an external interrupt source. SEG, LCD front plane 8. ATmega329/3290/649/6490 82 2552K–AVR–04/11 ...
Page 83
... LCDEN – – PCINT23 • PCINT22 • PCIE0 •LCDEN • PCIE0 •LCDEN • LCDPM LCDPM PCINT23 INPUT PCINT22 INPUT LCDSEG LCDSEG ATmega329/3290/649/6490 PH5/PCINT21/ PH4/PCINT20/ SEG38 SEG39 LCDEN LCDEN 0 0 LCDEN LCDEN – – PCINT21 • ...
Page 84
... DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.9 Alternate Functions of Port J Port J is only present in ATmega3290/6490. The alternate pin configuration is as follows: Table 13-27. Port J Pins Alternate Functions Port Pin PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 The alternate pin configuration is as follows: • ...
Page 85
... Table 13-29 relates the alternate functions of Port J to the overriding signals Figure 13-5 on page 65. PJ6/PCINT30/ SEG27 LCDEN 0 LCDEN – PCINT30 • PCIE0 •LCDEN • LCDPM LCDSEG ATmega329/3290/649/6490 PJ5/PCINT29/ PJ4/PCINT28/ SEG28 SEG29 LCDEN LCDEN 0 0 LCDEN LCDEN – – ...
Page 86
... Table 13-29. Overriding Signals for Alternate Functions in PH3:0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega329/3290/649/6490 86 PJ3/PCINT27/ PJ2/PCINT26/ SEG30 SEG31 LCDEN LCDEN 0 0 LCDEN LCDEN – – PCINT27 • PCINT26 • PCIE0 •LCDEN • ...
Page 87
... Read/Write Initial Value 13.4.6 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 13.4.7 PINB – Port B Input Pins Address Bit 0x03 (0x23) Read/Write Initial Value 2552K–AVR–04/11 ATmega329/3290/649/6490 JTD – – PUD R R for more details about this feature ...
Page 88
... PIND – Port D Input Pins Address Bit 0x09 (0x29) Read/Write Initial Value 13.4.14 PORTE – Port E Data Register Bit 0x0E (0x2E) Read/Write Initial Value 13.4.15 DDRE – Port E Data Direction Register Bit 0x0D (0x2D) Read/Write Initial Value ATmega329/3290/649/6490 PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 R/W R/W R/W R ...
Page 89
... DDRG – Port G Data Direction Register Bit 0x13 (0x33) Read/Write Initial Value 13.4.22 PING – Port G Input Pins Address Bit 0x12 (0x32) Read/Write Initial Value 13.4.23 PORTH – Port H Data Register Bit (0xDA) Read/Write Initial Value 2552K–AVR–04/11 ATmega329/3290/649/6490 PINE7 PINE6 PINE5 PINE4 R/W R/W R/W R/W N/A N/A N/A N/A 7 ...
Page 90
... R ( – DDJ6 DDJ5 DDJ4 R R/W R – PINJ6 PINJ5 PINJ4 R R/W R/W R/W 0 N/A N/A N/A 1. Register only available in ATmega3290/6490 DDH3 DDH2 DDH1 DDH0 R/W R/W R/W R PINH3 PINH2 PINH1 PINH0 R/W R/W R/W R/W N/A N/A N/A N PORTJ3 PORTJ2 PORTJ1 ...
Page 91
... The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter 2552K–AVR–04/11 ATmega329/3290/649/6490 “Pinout ATmega3290/6490” on page 2 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are 103. TCCRn ...
Page 92
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and pres- caler, see ATmega329/3290/649/6490 92 for details. The compare match event will also set the Compare Flag Table 14-1 are also used extensively throughout the document ...
Page 93
... Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 97. ATmega329/3290/649/6490 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 94
... WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom sig- nals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 14-3 Figure 14-3. Output Compare Unit, Block Diagram ATmega329/3290/649/6490 94 (See “Modes of Operation” on page shows a block diagram of the Output Compare unit. DATA BUS ...
Page 95
... PORT) that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin System Reset occur, the OC0A Register is reset to “0”. 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 14-4 shows a sim- 95 ...
Page 96
... A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits. ATmega329/3290/649/6490 96 COMnx1 Waveform COMnx0 ...
Page 97
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 2552K–AVR–04/11 ATmega329/3290/649/6490 (See “Compare Match Output Unit” on page Figure 14-8, 101. ...
Page 98
... In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in ATmega329/3290/649/6490 ...
Page 99
... OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum frequency of f feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 2552K–AVR–04/11 ATmega329/3290/649/6490 ...
Page 100
... The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare match between OCR0A and TCNT0 when the counter increments, and setting (or clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter ATmega329/3290/649/6490 100 1 2 ...
Page 101
... Figure 14-7 Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega329/3290/649/6490 f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low even though Figure 14-7. When the OCR0A value is MAX the ...
Page 102
... Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 14-10 Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f clk clk (clk I/O TCNTn OCRnx OCFnx ATmega329/3290/649/6490 102 I/O Tn /8) MAX - 1 shows the setting of OCF0A in all modes except CTC mode. I/O Tn /8) OCRnx - 1 /8) clk_I/O MAX BOTTOM OCRnx ...
Page 103
... OCF0A and the clearing of TCNT0 in CTC mode. caler (f /8) clk_I/O I/O Tn /8) I/O TOP - FOC0A WGM00 COM0A1 COM0A0 W R/W R/W R 97. ATmega329/3290/649/6490 TOP BOTTOM TOP WGM01 CS02 CS01 CS00 R/W R/W R/W R Table 14-2 and “Modes of Operation” ...
Page 104
... CTC mode (non-PWM). Table 14-3. COM0A1 Table 14-4 mode. Table 14-4. COM0A1 Note: Table 14-5 rect PWM mode. ATmega329/3290/649/6490 104 Waveform Generation Mode Bit Description WGM01 WGM00 Timer/Counter (CTC0) (PWM0) Mode of Operation 0 0 Normal 0 1 PWM, Phase Correct 1 0 CTC ...
Page 105
... External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge TCNT0[7:0] R/W R/W R/W R OCR0A[7:0] R/W R/W R/W R ATmega329/3290/649/6490 (1) “Phase Correct PWM Mode” R/W R/W R/W R R/W R/W R/W R TCNT0 OCR0 105 ...
Page 106
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter- rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. ATmega329/3290/649/6490 106 ...
Page 107
... Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk clk I/O Synchronization ATmega329/3290/649/6490 /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O Figure 15-1 ) ...
Page 108
... When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 ATmega329/3290/649/6490 108 < f /2) given a 50/50% duty cycle. Since the edge detector uses ...
Page 109
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 2552K–AVR–04/11 ATmega329/3290/649/6490 109 ...
Page 110
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in Timer/Counter1 module. ATmega329/3290/649/6490 110 “Pinout ATmega3290/6490” on page “Register Description” on page “Power Reduction Register” on page 37 Figure 16-1. For the actual 2. CPU accessible I/O Reg- 132 ...
Page 111
... PWM or variable frequency output on the Output Compare pin (OC1A/B). 2552K–AVR–04/11 Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1-1 on page 2, Timer/Counter1 pin placement and description. ATmega329/3290/649/6490 (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...
Page 112
... WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. ATmega329/3290/649/6490 112 119.. The compare match event will also set the Compare Match 207.) The Input Capture unit includes a digital filtering unit (Noise Definitions of Timer/Counter values. ...
Page 113
... Therefore, when both 2552K–AVR–04/11 (1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1; ... 1. See “About Code Examples” on page 9. ATmega329/3290/649/6490 113 ...
Page 114
... SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATmega329/3290/649/6490 114 (1) (1) 1. See “About Code Examples” on page 9. 2552K–AVR–04/11 ...
Page 115
... TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See “About Code Examples” on page 9. ATmega329/3290/649/6490 115 ...
Page 116
... Clock Select bits (CS12:0). When no clock source is selected (CS12 the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of ATmega329/3290/649/6490 116 “Timer/Counter0 and Timer/Counter1 Prescalers” on page shows a block diagram of the counter and its surroundings. ...
Page 117
... Operation” on page DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn ATmega329/3290/649/6490 123. Figure 16-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...
Page 118
... In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter- rupt handler routine as possible. Even though the Input Capture interrupt has relatively high ATmega329/3290/649/6490 118 113. ...
Page 119
... Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. 2552K–AVR–04/11 ATmega329/3290/649/6490 (See “Modes of Operation” on page shows a block diagram of the Output Compare unit. The small “n” in the register and 123 ...
Page 120
... Force Output Compare (FOC1x) bit. Forcing compare match will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated real compare match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or toggled). ATmega329/3290/649/6490 120 TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf ...
Page 121
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 2552K–AVR–04/11 ATmega329/3290/649/6490 121 ...
Page 122
... The design of the Output Compare pin logic allows initialization of the OC1x state before the out- put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. The COM1x1:0 bits have no effect on the Input Capture unit. ATmega329/3290/649/6490 122 Waveform D ...
Page 123
... OCR1A (WGM13 the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This 2552K–AVR–04/11 ATmega329/3290/649/6490 Table 16-2 on page 132. For fast PWM mode refer to 122.) “ ...
Page 124
... PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare ATmega329/3290/649/6490 124 1 2 ...
Page 125
... Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. 2552K–AVR–04/11 ATmega329/3290/649/6490 ( TOP log R ...
Page 126
... The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while counting up, and set on the compare match while counting down. In inverting Output Compare mode, the operation is ATmega329/3290/649/6490 126 Table 16-3 on page f ...
Page 127
... When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. 2552K–AVR–04/11 ATmega329/3290/649/6490 ( ) TOP ...
Page 128
... PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see 8 and Figure ATmega329/3290/649/6490 128 f OCnxPCPWM 16-9). Figure 16-8 ...
Page 129
... Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 16-9 cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. 2552K–AVR–04/11 ATmega329/3290/649/6490 log R = ---------------------------------- - PFCPWM Figure 16-9 ...
Page 130
... The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling (clk TCNTn OCRnx OCFnx Figure 16-11 ATmega329/3290/649/6490 130 f OCnxPFCPWM Figure 16-10 clk I/O clk Tn ...
Page 131
... FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. ATmega329/3290/649/6490 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 ...
Page 132
... OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 16-2. COM1A1/COM1B1 ATmega329/3290/649/6490 132 clk I/O clk Tn ...
Page 133
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 126. Table 16-5. Modes of operation supported by the Timer/Counter ATmega329/3290/649/6490 (1) Description Normal port operation, OC1A/OC1B disconnected. WGM13 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation) ...
Page 134
... When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. ATmega329/3290/649/6490 134 (1) WGM10 ...
Page 135
... External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – – R/W R ATmega329/3290/649/6490 – – – – Figure TCCR1C 135 ...
Page 136
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. ATmega329/3290/649/6490 136 7 6 ...
Page 137
... ICIE1 – R (See “Interrupts” on page 49.) is executed when the ICF1 Flag, located in TIFR1, is set. (See “Interrupts” on page (See “Interrupts” on page 49.) is executed when the TOV1 Flag, located in TIFR1, is set. ATmega329/3290/649/6490 ICR1[15:8] ICR1[7:0] R/W R/W R/W R ...
Page 138
... The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega329/3290/649/6490 138 ...
Page 139
... I/O pins, refer to isters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 17-1. 8-bit Timer/Counter Block Diagram 2552K–AVR–04/11 ATmega329/3290/649/6490 “Pinout ATmega3290/6490” on page “Register Description” on page TCCRnx count clear Control Logic ...
Page 140
... Prescaler” on page 17.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 17-2 shows a block diagram of the counter and its surrounding environment. ATmega329/3290/649/6490 140 ). T2 for details. The compare match event will also set the Compare Table 17-1 are also used extensively throughout the section. ...
Page 141
... Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 145. 145). shows a block diagram of the Output Compare unit. ATmega329/3290/649/6490 TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler top TOSC1 ...
Page 142
... Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is counting down. ATmega329/3290/649/6490 142 DATA BUS OCRnx ...
Page 143
... Normal mode. The OC2A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2A1:0 bits are not double buffered together with the compare value. Changing the COM2A1:0 bits will take effect immediately. 2552K–AVR–04/11 ATmega329/3290/649/6490 143 ...
Page 144
... The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2A1 tells the Waveform Generator that no action on the OC2A Register performed on the next compare match. For compare output actions in the non-PWM modes refer to on page ATmega329/3290/649/6490 144 Waveform Generator I/O See “ ...
Page 145
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. 2552K–AVR–04/11 ATmega329/3290/649/6490 (See “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page 144.). 149. ...
Page 146
... In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast ATmega329/3290/649/6490 146 1 ...
Page 147
... OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 17-6. The TCNT2 value is in the timing diagram shown as a his- 1 ...
Page 148
... The actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register at the compare match between OCR2A and TCNT2 when the counter increments, and setting (or clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter ATmega329/3290/649/6490 148 1 2 ...
Page 149
... Timer/Counter operation. The figure shows the clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn shows the same timing data, but with the prescaler enabled. ATmega329/3290/649/6490 f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low even though Figure 17-7. When the OCR2A value is MAX the should be replaced by I/O ...
Page 150
... Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (f TCNTn Figure 17-10 Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f (clk TCNTn Figure 17-11 Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- (clk TCNTn ATmega329/3290/649/6490 150 clk I/O clk Tn (clk /8) I/O MAX - 1 TOVn shows the setting of OCF2A in all modes except CTC mode. ...
Page 151
... When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four 2552K–AVR–04/11 ATmega329/3290/649/6490 151 ...
Page 152
... TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. If apply- ing an external clock on TOSC1, the EXCLK bit in ASSR must be set. ATmega329/3290/649/6490 152 ) again becomes active, TCNT2 will read as the previous ...
Page 153
... Fast PWM 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega329/3290/649/6490 /8, clk T2S T2S as well as 0 (stop) may be selected. T2S ...
Page 154
... Note: Table 17-5 rect PWM mode. Table 17-5. COM2A1 Note: ATmega329/3290/649/6490 154 Table 17-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits Compare Output Mode, non-PWM Mode COM2A0 Description 0 Normal port operation, OC2A disconnected. 1 Toggle OC2A on compare match. 0 Clear OC2A on compare match. ...
Page 155
... Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. 2552K–AVR–04/11 ATmega329/3290/649/6490 Clock Select Bit Description CS21 CS20 ...
Page 156
... When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. ATmega329/3290/649/6490 156 7 6 ...
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... If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the chronization Mode” on page 108 2552K–AVR–04/11 ATmega329/3290/649/6490 – ...
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... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega329/3290/649/6490 and peripheral devices or between several AVR devices. A simpli- fied block diagram of the Serial Peripheral Interface is shown in The PRSPI bit in SPI module. Figure 18-1. SPI Block Diagram ...
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... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high period should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure SHIFT ENABLE 18-2. The sys- ...
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... When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 18-1. Pin MOSI MISO SCK SS Note: ATmega329/3290/649/6490 160 Table 18-1. For more details on automatic port overrides, refer to 65. (1) SPI Pin Overrides Direction, Master SPI User Defined Input ...
Page 161
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 9. ATmega329/3290/649/6490 161 ...
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... DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR; } Note: ATmega329/3290/649/6490 162 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( See “About Code Examples” on page 9. 2552K–AVR–04/11 ...
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... Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi- bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. 2552K–AVR–04/11 ATmega329/3290/649/6490 163 ...
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... This is clearly seen by summarizing Table 18-3 Table 18-2. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 18-3. SPI Transfer Format with CPHA = 0 ATmega329/3290/649/6490 164 Figure 18-4. Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 18-4, as done below: CPOL Functionality ...
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... MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit SPIE SPE DORD MSTR R/W R/W R/W R ATmega329/3290/649/6490 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit CPOL CPHA SPR1 SPR0 R/W R/W R/W R ...
Page 166
... These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f shown in the following table: Table 18-5. SPI2X ATmega329/3290/649/6490 166 Figure 18-3 and Figure 18-4 CPOL Functionality ...
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... SPI Data Register. • Bit 5..1 – Reserved Bits These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
Page 168
... A simplified block diagram of the USART Transmitter is shown in I/O Registers and I/O pins are shown in bold. The Power Reduction USART bit, PRUSART0 must be written to zero to enable USART0 module. Figure 19-1. USART Block Diagram Note: ATmega329/3290/649/6490 168 (1) UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER ...
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... XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 19-2 2552K–AVR–04/11 ATmega329/3290/649/6490 shows a block diagram of the clock generation logic. Figure 19-1) if the Buffer Registers ...
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... Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCK bits. Table 19-1 ing the UBRRn value for each mode of operation using an internally generated clock source. ATmega329/3290/649/6490 170 UBRR fosc UBRR+1 ...
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... Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRnH and UBRRnL Registers, (0-4095) 186). Figure 19-2 for details. depends on the stability of the system clock source therefore recommended to osc ATmega329/3290/649/6490 Equation for Calculating (1) UBRRn Value f f OSC OSC ...
Page 172
... If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 19-4 optional. ATmega329/3290/649/6490 172 UCPOL = 1 XCK RxD / TxD ...
Page 173
... even n 1 – ⊕ odd n 1 – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n ATmega329/3290/649/6490 FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 174
... Set baud rate */ UBRR0H = (unsigned char)(ubrr>>8); UBRR0L = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSR0B = (1<<RXEN0)|(1<<TXEN0); /* Set frame format: 8data, 2stop bit */ UCSR0C = (1<<USBS0)|(3<<UCSZ00); } ATmega329/3290/649/6490 174 1. See “About Code Examples” on page 9. (1) UBRR0H, r17 UBRR0L, r16 r16, (1<<RXEN0)|(1<<TXEN0) UCSR0B,r16 r16, (1< ...
Page 175
... UCSR0A,UDRE0 rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR0,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSR0A & (1<<UDRE0 Put data into buffer, sends the data */ UDR0 = data; 1. See “About Code Examples” on page 9. ATmega329/3290/649/6490 175 ...
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... Put data into buffer, sends the data */ UDR0 = data; } Notes: The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as for example synchronization. ATmega329/3290/649/6490 176 (1)(2) UCSR0B,TXB80 UCSR0B,TXB80 UDR0,r16 (1)(2) ...
Page 177
... USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock. 2552K–AVR–04/11 ATmega329/3290/649/6490 177 ...
Page 178
... Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. ATmega329/3290/649/6490 178 (1) ...
Page 179
... Get status and 9th bit, then data */ /* from buffer */ status = UCSR0A; resh = UCSR0B; resl = UDRn error, return - status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 9. ATmega329/3290/649/6490 179 ...
Page 180
... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. ATmega329/3290/649/6490 180 “Parity Bit Calculation” on page 173 and “ ...
Page 181
... RxD line is idle (i.e., no communication activity). 2552K–AVR–04/11 (1) sbis UCSR0A, RXC0 ret in r16, UDR0 rjmp USART_Flush (1) unsigned char dummy; while ( UCSR0A & (1<<RXC0) ) dummy = UDR0; 1. See “About Code Examples” on page 9. ATmega329/3290/649/6490 Figure 19-5 181 ...
Page 182
... RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 19-7 of the next frame. ATmega329/3290/649/6490 182 RxD IDLE 0 ...
Page 183
... R is the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 19-3 list the maximum receiver baud rate error that can be tolerated. Note ATmega329/3290/649/6490 STOP 1 (A) ( ...
Page 184
... The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRRn value that gives an acceptable low error can be used if possible. ATmega329/3290/649/6490 184 Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode ...
Page 185
... Transmitter and Receiver uses the same character size set- ting 8-bit character frames are used, the Transmitter must be set to use two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type. 2552K–AVR–04/11 ATmega329/3290/649/6490 185 ...
Page 186
... Max. 62.5kbps 1. UBRR = 0, Error = 0.0% ATmega329/3290/649/6490 186 183). The error values are calculated using the following equation: BaudRate ⎛ Error[%] = ------------------------------------------------------- - 1 ⎝ 1.8432MHz osc U2Xn = 0 Error UBRRn Error UBRRn 0.2% 47 0.0% 0.2% 23 ...
Page 187
... Max. 230.4kbps 460.8kbps 1. UBRR = 0, Error = 0.0% 2552K–AVR–04/11 ATmega329/3290/649/6490 f = 4.0000MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0.0% 16 2.1% 34 0.0% 12 0.2% 25 0.0% 8 -3.5% 16 0.0% 6 -7.0% 12 0. ...
Page 188
... Max. 0.5Mbps 1. UBRR = 0, Error = 0.0% ATmega329/3290/649/6490 188 11.0592 f = osc U2Xn = 0 Error UBRRn Error UBRRn -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – – 0.0% – – ...
Page 189
... U2Xn = 0 Error UBRRn Error UBRRn 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – – 0.0% – – 2Mbps 1.152Mbps ATmega329/3290/649/6490 f = 20.0000MHz osc U2Xn = 1 U2Xn = 0 Error UBRRn Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0.0% 86 -0.2% 119 0.0% 64 0.2% 79 0.0% 42 0.9% 59 0.0% 32 -1.4% 39 0.0% 21 -1.4% 29 0.0% 15 1.7% 19 0.0% 10 -1. ...
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... The TXCn Flag bit is auto- matically cleared when a transmit complete interrupt is executed can be cleared by writing a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see description of the TXCIEn bit). ATmega329/3290/649/6490 190 7 6 ...
Page 191
... Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in UCSRnA is set. 2552K–AVR–04/11 ATmega329/3290/649/6490 “Multi-processor Communication Mode” on page 7 6 ...
Page 192
... Must be written before writing the low bits to UDRn. 19.11.4 UCSRnC – USART Control and Status Register n C Bit Read/Write Initial Value • Bit 6 – UMSELn: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 19-8. ATmega329/3290/649/6490 192 – UMSELn UPMn1 ...
Page 193
... USBSn 0 1 UCSZn2 UCSZn1 ATmega329/3290/649/6490 Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity Stop Bit(s) 1-bit 2-bit UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit ...
Page 194
... UBRRnL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler. ATmega329/3290/649/6490 194 Transmitted Data Changed ...
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... Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. 2552K–AVR–04/11 ATmega329/3290/649/6490 “Pinout ATmega3290/6490” on page ...
Page 196
... The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. ATmega329/3290/649/6490 196 Bit7 Bit6 ...
Page 197
... The overflow interrupt will wake up the processor set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. 2552K–AVR–04/11 ( Reference ) MSB MSB ATmega329/3290/649/6490 LSB LSB 8 E 197 ...
Page 198
... The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. ATmega329/3290/649/6490 198 sts ...
Page 199
... USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 ; LSB sts USICR,r17 lds r16,USIDR ldi r16,(1<<USIWM0)|(1<<USICS1) sts USICR,r16 sts USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 lds r16, USISR sbrs r16, USIOIF rjmp SlaveSPITransfer_loop lds r16,USIDR ret ATmega329/3290/649/6490 199 ...
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... Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORT Register. ATmega329/3290/649/6490 200 Bit7 Bit6 ...