ATmega3290 Atmel Corporation, ATmega3290 Datasheet
ATmega3290
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ATmega3290 Summary of contents
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... Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – Segment LCD Driver (ATmega329/ATmega649) – Segment LCD Driver (ATmega3290/ATmega6490) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – ...
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... Pin Configurations Figure 1-1. Pinout ATmega3290/6490 1 LCDCAP 2 (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 5 (AIN1/PCINT3) PE3 6 (USCK/SCL/PCINT4) PE4 7 (DI/SDA/PCINT5) PE5 8 (DO/PCINT6) PE6 9 (CLKO/PCINT7) PE7 VCC 10 GND 11 12 DNC 13 (PCINT24/SEG35) PJ0 14 (PCINT25/SEG34) PJ1 15 DNC 16 DNC 17 DNC DNC 18 19 (SS/PCINT8) PB0 20 (SCK/PCINT9) PB1 21 (MOSI/PCINT10) PB2 ...
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Figure 1-2. Pinout ATmega329/649 LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) ...
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Overview The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architec- ture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs approaching 1 MIPS per MHz allowing the system designer ...
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The Atmel ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while ...
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... Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490 The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes, pin count and pinout. devices. Table 2-1. Device ATmega329 ATmega3290 ATmega649 ATmega6490 2.3 Pin Descriptions The following section describes the I/O-pin special functions. 2.3 Digital supply voltage. ...
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Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C ...
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... As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3290/6490 as listed on page 75. ...
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LCDCAP An external capacitor (typical > 470nF) must be connected to the LCDCAP pin as shown in ure 23-2. This capacitor acts as a reservoir for LCD power (V ripple Resources A comprehensive set of development ...
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AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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AVR Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register ...
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Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 6.5 General Purpose Register File The Register File is optimized for the ...
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The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 6-4 vard architecture and the fast-access Register ...
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RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep ...
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AVR ATmega329/3290/649/6490 Memories This section describes the different memories in the ATmega329/3290/649/6490. The Atmel ® AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega329/3290/649/6490 features an EEPROM Memory for ...
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SRAM Data Memory Figure 7-2 The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instruc- tions. For the Extended I/O space ...
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Figure 7-3. 7.3 EEPROM Data Memory The ATmega329/3290/649/6490 contains 1/2K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...
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Power-down entirely therefore recommended to verify that the EEPROM write operation is completed before entering Power-down. 7.3.3 Preventing EEPROM Corruption During periods of low V too low for the CPU and the ...
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Register Description 7.5.1 EEARH and EEARL – The EEPROM Address Register Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:11 – Reserved Bits These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero. ...
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If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for ...
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The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob- ally) so that no interrupts will occur during execution of these functions. ...
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Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 7.5.4 GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 7.5.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write ...
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System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter ...
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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. C1 and C2 should always be ...
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Table 8-4. CKSEL0 Note: 8.4 Low-frequency Crystal Oscillator To use a 32.768kHz watch crystal as the clock source for the device, the low-frequency crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” ...
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This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 8-7 on page hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy ...
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External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 8-3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 8-3. When this ...
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If the System Clock Prescaler is used the divided system clock that is output when the CKOUT Fuse is programmed. 8.8 Timer/Counter Oscillator ATmega329/3290/649/6490 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 ...
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Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM or Flash ...
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Table 8-11. CLKPS3 ATmega329/3290/649/6490 34 Clock Prescaler Select CLKPS2 CLKPS1 CLKPS0 ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system ...
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If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, ...
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Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, ...
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Write one to the JTD bit in MCUCSR. The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data. If the hardware connected to the TDO pin does not ...
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PRR – Power Reduction Register Bit (0x64) Read/Write Initial Value • Bits Reserved bits These bits are reserved bits in ATmega329/3290/649/6490 and will always read as zero. • Bit 4 - PRLCD: Power Reduction LCD ...
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System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 10-1. Reset Logic BODLEVEL [1..0] 10.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to ...
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Figure 10-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 10.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is ...
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Figure 10-5. Brown-out Reset During Operation 10.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out ...
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ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 10.8 Watchdog Timer The Watchdog Timer is clocked from a ...
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Table 10-2. WDP2 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so ...
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Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 10.9.1 Safety Level 1 In this mode, the Watchdog Timer ...
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Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a ...
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... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 3. PCINT2 and PCINT3 are only present in ATmega3290 and ATmega6490. ATmega329/3290/649/6490 278. ...
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Table 11-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is ...
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A 0x002 C 0x002 E 0x003 0 ; 0x003 2 0x003 3 0x003 4 0x003 5 0x003 6 0x003 7 When the BOOTRST Fuse is unprogrammed, the Boot section size set ...
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Main program start 0x3801/0x7801 0x3802/0x7802 0x3803/0x7803 0x3804/0x7804 0x3805/0x7805 When the BOOTRST Fuse is programmed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before ...
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Self-Programming” on page 278 tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing ...
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External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT30..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30..0 pins are configured as outputs. This feature provides ...
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Register Description 12.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) Read/Write Initial Value • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 ...
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Bit 5 – PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 ...
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... PCINT30 PCINT29 PCINT28 R R/W R PCINT23 PCINT22 PCINT21 PCINT20 R/W R/W R/W R PCMSK3 and PCMSK2 are only present in ATmega3290/6490. ATmega329/3290/649/6490 PCINT27 PCINT26 PCINT25 PCINT24 R/W R/W R/W R PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R PCMSK3 ...
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PCMSK1 – Pin Change Mask Register 1 Bit (0x6C) Read/Write Initial Value • Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8 Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is ...
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I/O-Ports 13.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ...
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The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin ...
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Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS ATmega329/3290/649/6490 62 SYSTEM CLK XXX SYNC LATCH PINxn r17 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF 2552K–AVR–04/11 ...
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...
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Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out ; Insert nop for synchronization nop ; Read port pins in ... C Code Example unsigned char i; ... ...
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Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable ...
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... Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog This is the Analog Input/output to/from alternate Input/Output functions. The signal is connected directly to the pad, and can be used bi-directionally. “Pinout ATmega3290/6490” on page 2 for details. Fig- and “Pinout 2552K–AVR–04/11 ...
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Alternate Functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller. Table 13-3. Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Table 13-4 shown in Table 13-4. Signal ...
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Table 13-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-6. Port Pin PB7 PB6 PB5 PB4 PB3 ...
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PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external interrupt source. • OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare ...
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SS/PCINT8 – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0 Slave, the SPI is activated ...
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Table 13-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.3 Alternate Functions of Port C The Port C has an alternate function as SEG for the LCD Controller. Table 13-9. Port Pin PC7 PC6 ...
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Table 13-10. Overriding Signals for Alternate Functions in PC7:PC4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-12. Port D Pins Alternate Functions (SEG refers to 100-pin/64-pin pinout) Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate ...
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Table 13-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE ...
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Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-15. Port E Pins Alternate Functions Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 • PCINT7 – Port E, Bit 7 ...
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XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 oper- ates in ...
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Table 13-17. Overriding Signals for Alternate Functions in PE3:PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 13.3.6 Alternate Functions of Port F The Port F has an alternate function as analog input for ...
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TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be ...
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Table 13-20. Overriding Signals for Alternate Functions in PF3:PF0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.7 Alternate Functions of Port G The alternate pin configuration is as follows: Table 13-21. Port G Pins ...
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SEG – Port G, Bit 2 SEG, LCD front plane 4/4. • SEG – Port G, Bit 1 SEG, Segment driver 17/13. • SEG – Port G, Bit 0 SEG, LCD front plane 18/14. Table 13-21 shown in Table ...
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... DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.8 Alternate Functions of Port H Port H is only present in ATmega3290/6490. The alternate pin configuration is as follows: Table 13-24. Port H Pins Alternate Functions Port Pin PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 The alternate pin configuration is as follows: • ...
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PCINT21/SEG – Port H, Bit 5 PCINT21, Pin Change Interrupt Source 21: The PH5 pin can serve as an external interrupt source. SEG, LCD front plane 38. • PCINT20/SEG – Port H, Bit 4 PCINT20, Pin Change Interrupt Source ...
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PCINT17/SEG – Port H, Bit 1 PCINT17, Pin Change Interrupt Source 17: The P1 pin can serve as an external interrupt source. SEG, LCD front plane 9. • PCINT16/SEG – Port H, Bit 0 PCINT16, Pin Change Interrupt Source ...
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... DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.9 Alternate Functions of Port J Port J is only present in ATmega3290/6490. The alternate pin configuration is as follows: Table 13-27. Port J Pins Alternate Functions Port Pin PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 The alternate pin configuration is as follows: • ...
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PCINT28/SEG – Port J, Bit 4 PCINT28, Pin Change Interrupt Source 28: The PE28 pin can serve as an external interrupt source. SEG, LCD front plane 29. • PCINT27/SEG – Port J, Bit 3 PCINT27, Pin Change Interrupt Source ...
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Table 13-29. Overriding Signals for Alternate Functions in PH3:0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega329/3290/649/6490 86 PJ3/PCINT27/ PJ2/PCINT26/ SEG30 SEG31 LCDEN LCDEN 0 0 LCDEN LCDEN ...
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Register Description 13.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the ...
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PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 13.4.9 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 13.4.10 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial ...
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PINE – Port E Input Pins Address Bit 0x0C (0x2C) Read/Write Initial Value 13.4.17 PORTF – Port F Data Register Bit 0x11 (0x31) Read/Write Initial Value 13.4.18 DDRF – Port F Data Direction Register Bit 0x10 (0x30) Read/Write Initial ...
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... R ( – DDJ6 DDJ5 DDJ4 R R/W R – PINJ6 PINJ5 PINJ4 R R/W R/W R/W 0 N/A N/A N/A 1. Register only available in ATmega3290/6490 DDH3 DDH2 DDH1 DDH0 R/W R/W R/W R PINH3 PINH2 PINH1 PINH0 R/W R/W R/W R/W N/A N/A N/A N PORTJ3 PORTJ2 PORTJ1 ...
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... The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter 2552K–AVR–04/11 ATmega329/3290/649/6490 “Pinout ATmega3290/6490” on page 2 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are 103. TCCRn ...
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The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Register (OCR0A) is ...
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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 14-2 shows a block diagram of the counter and its surroundings. Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear ...
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Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom sig- nals are used by the Waveform Generator for handling the ...
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The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ering is disabled. The double buffering synchronizes the update ...
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Figure 14-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out- put) ...
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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits. The Compare Output mode ...
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Figure 14-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 14-6. Fast PWM Mode, Timing Diagram TCNTn OCn OCn ...
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Phase Correct PWM Mode The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM ...
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The PWM frequency for the output when using phase correct PWM can be calcu- lated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register ...
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Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 14-10 Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f clk clk (clk I/O TCNTn OCRnx OCFnx ATmega329/3290/649/6490 102 I/O Tn /8) MAX ...
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Figure 14-11 Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx 14.9 Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bit ...
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Table 14-2. Mode Note: • Bit 5:4 – COM0A1:0: Compare Match Output Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides ...
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Table 14-5. COM0A1 Note: • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 14-6. CS02 ...
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The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0A pin. 14.9.4 ...
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Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 15.0.1 Internal Clock Source The Timer/Counter can be clocked directly ...
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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...
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When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset ...
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... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in Timer/Counter1 module. ATmega329/3290/649/6490 110 “Pinout ATmega3290/6490” on page “Register Description” on page “Power Reduction Register” on page 37 Figure 16-1. For the actual 2. CPU accessible I/O Reg- 132 ...
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Figure 16-1. 16-bit Timer/Counter Block Diagram Note: 16.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
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Compare Units” on page Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture ...
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Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit ...
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The following code examples show how atomic read of the TCNT1 Register contents. Reading any ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...
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Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter ...
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The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves ...
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Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading ...
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Using the Input Capture unit in any mode of operation when the TOP value (resolution) ...
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Figure 16-4. Output Compare Unit, Block Diagram The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is ...
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Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized ...
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Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the OC1x Register ...
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It also simplifies the opera- tion of counting external events. The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ...
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Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor- rect and phase and frequency correct ...
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The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with ...
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The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM ...
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Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in TOP actively while the Timer/Counter is running in the phase correct mode ...
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The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A ...
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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively ...
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Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 16-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...
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Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A • Bit 5:4 ...
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Table 16-3 PWM mode. Table 16-3. COM1A1/COM1B1 Note: Table 16-4 correct or the phase and frequency correct, PWM mode. Table 16-4. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B ...
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Table 16-5. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...
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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 16.11.4 TCNT1H and TCNT1L – Timer/Counter1 ...
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ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator ...
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TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register ...
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... I/O pins, refer to isters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 17-1. 8-bit Timer/Counter Block Diagram 2552K–AVR–04/11 ATmega329/3290/649/6490 “Pinout ATmega3290/6490” on page “Register Description” on page TCCRnx count clear Control Logic ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter- rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask ...
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Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 17-3. Output Compare Unit, Block Diagram The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...
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The setup of the OC2A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2A value is to use the Force Output Com- pare (FOC2A) strobe bit in ...
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Compare Match Output Unit The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Generator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare match. Also, the COM2A1:0 bits control the OC2A ...
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A change of the COM2A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2A strobe bits. 17.7 Modes ...
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Figure 17-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 17-6. Fast PWM Mode, ...
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Phase Correct PWM Mode The phase correct PWM mode (WGM21 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM ...
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The PWM frequency for the output when using phase correct PWM can be calcu- lated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the ...
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Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (f TCNTn Figure 17-10 Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f (clk TCNTn Figure 17-11 Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- (clk ...
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Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching ...
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SLEEP. • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading ...
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For Timer/Counter2, the possible prescaled selections are: clk clk /128, clk T2S Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre- dictable prescaler. 17.11 Register Description 17.11.1 TCCR2A – Timer/Counter Control ...
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When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM21:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 17-3. COM2A1 Table 17-4 mode. Table 17-4. ...
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Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 17-6. Table 17-6. CS22 17.11.2 TCNT2 – Timer/Counter Register ...
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Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil- lator 1 (TOSC1) pin. ...
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TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 0x17 (0x37) Read/Write Initial Value • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data ...
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SPI – Serial Peripheral Interface 18.1 Features The ATmega329/3290/649/6490 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • ...
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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 18-1. Pin MOSI MISO SCK SS Note: ATmega329/3290/649/6490 160 Table 18-1. For more details on automatic ...
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The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi out ; Enable SPI ldi out ret SPI_SlaveReceive: ...
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SS Pin Functionality 18.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in 18-3 and nal, ensuring sufficient time ...
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Figure 18-4. SPI Transfer Format with CPHA = 1 18.5 Register Description 18.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be ...
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Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to marized below: Table 18-3. • Bit 2 – ...
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SPSR – SPI Status Register Bit 0x2D (0x4D) Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is ...
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USART0 19.1 Features The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation ...
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The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation logic consists of synchronization logic for ...
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Figure 19-2. Clock Generation Logic, Block Diagram DDR_XCK Signal description: txclk rxclk xcki operation. xcko fosc 19.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. ...
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Table 19-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f OSC UBRRn Some examples of UBRRn values for some system clock frequencies are found in (see page ...
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Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is ...
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Figure 19-4. Frame Formats St ( IDLE be The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that ...
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Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXCn Flag can be used to check that the Transmitter has completed all ...
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More advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization ...
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The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into ...
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Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether ...
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Receiving Frames with Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted ...
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The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example ...
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Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...
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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until ...
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Figure 19-5. Start Bit Sampling Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 ...
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Figure 19-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...
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Table 19-2. # (Data+Parity Bit) Table 19-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...
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Multi-processor Communication Mode Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the ...
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Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 19.10 ...
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Table 19-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 ...
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Table 19-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 ...
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Table 19-7. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 ...
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Register Description 19.11.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...
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Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn ...
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Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt ...
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Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...
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Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and ...
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... Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. 2552K–AVR–04/11 ATmega329/3290/649/6490 “Pinout ATmega3290/6490” on page ...
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The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count ...
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Figure 20-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK The Three-wire mode timing is shown in Figure 20-3. At the top of the figure is a USCK cycle ref- erence. One bit is shifted into the USI Shift Register (USIDR) ...
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SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: SPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and ...
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The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4): SPITransfer_Fast: ret 20.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI ...
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The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO is configured as output and USCK pin is configured as input in the DDR Register. The value stored in register r16 prior ...