ATmega3290P Atmel Corporation, ATmega3290P Datasheet - Page 148

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ATmega3290P

Manufacturer Part Number
ATmega3290P
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega3290P

Flash (kbytes)
32 Kbytes
Pin Count
100
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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8021G–AVR–03/11
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in
togram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2A and TCNT2.
Figure 17-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.
Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM2A1:0 to three (See
OC2A value will only be visible on the port pin if the data direction for the port pin is set as out-
put. The PWM waveform is generated by setting (or clearing) the OC2A Register at the compare
match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at the timer
clock cycle the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0
bits.)
TCNTn
OCnx
OCnx
Period
1
Figure
2
17-6. The TCNT2 value is in the timing diagram shown as a his-
3
f
OCnxPWM
4
5
=
----------------- -
N 256
f
clk_I/O
6
ATmega329P/3290P
Table 17-4 on page
7
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
156). The actual
148

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