ATmega3290P Atmel Corporation, ATmega3290P Datasheet - Page 228

• Manufacturer Part Number: ATmega3290P
• Manufacturer: Atmel Corporation

Specifications of ATmega3290P

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.9.3
22.9.3.1
22.9.3.2
22.9.4
8021G–AVR–03/11
ADCL and ADCH – The ADC Data Register
ADCSRB – ADC Control and Status Register B
ADLAR = 0
ADLAR = 1
Table 22-5.
When an ADC conversion is complete, the result is found in these two registers. When ADCL is
read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x7B)
Read/Write
Initial Value
223.
ADPS2
1
1
1
ADC Prescaler Selections (Continued)
ADC7
ADC9
ADC1
15
15
R
R
–
7
0
0
R
R
7
0
0
R
7
–
0
ADC6
ADC8
ADC0
ACME
R/W
14
14
ADPS1
R
R
R
R
–
6
0
0
6
0
0
6
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
R
5
–
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
0
–
4
0
R
4
–
0
ADPS0
1
0
1
ADC3
ADC5
11
11
R
R
–
3
0
0
R
R
R
–
3
0
0
3
–
0
ATmega329P/3290P
ADTS2
ADC2
ADC4
R/W
10
10
R
R
–
2
0
0
R
R
–
2
0
0
2
0
”ADC Conversion Result” on
ADTS1
ADC9
ADC1
ADC3
Division Factor
R/W
R
R
9
1
0
0
R
R
9
–
1
0
0
1
0
128
32
64
ADTS0
ADC8
ADC0
ADC2
R/W
8
0
R
R
0
0
R
R
0
0
8
–
0
0
0
ADCSRB
ADCH
ADCL
ADCH
ADCL
228