ATmega3290P Atmel Corporation, ATmega3290P Datasheet - Page 27

• Manufacturer Part Number: ATmega3290P
• Manufacturer: Atmel Corporation

Specifications of ATmega3290P

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8. System Clock and Clock Options
8.1
8.1.1
8.1.2
8.1.3
8021G–AVR–03/11
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
I/O
Figure 8-1
the clocks need not be active at a given time. In order to reduce power consumption, the clocks
to modules not being used can be halted by using different sleep modes, as described in
Management and Sleep Modes” on page
Figure 8-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that start condition detection in the USI module is carried out asynchro-
nously when clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
CPU
FLASH
LCD Controller
presents the principal clock systems in the Atmel
Clock Distribution
I/O
is halted, enabling USI start condition detection in all sleep modes.
Timer/Counter
Timer/Counter
Asynchronous
Oscillator
General I/O
Modules
External Clock
clk
clk
ASY
I/O
37. The clock systems are detailed below.
Control Unit
AVR Clock
Multiplexer
Clock
Source clock
Oscillator
Crystal
ATmega329P/3290P
CPU Core
clk
clk
Reset Logic
CPU
FLASH
®
AVR
Crystal Oscillator
Watchdog clock
Low-frequency
®
and their distribution. All of
Watchdog Timer
RAM
Watchdog
Oscillator
Calibrated RC
Flash and
EEPROM
Oscillator
”Power
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