ATmega3290P Atmel Corporation, ATmega3290P Datasheet - Page 28

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ATmega3290P

Manufacturer Part Number
ATmega3290P
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega3290P

Flash (kbytes)
32 Kbytes
Pin Count
100
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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8.1.4
8.1.5
8.2
8.3
8021G–AVR–03/11
Clock Sources
Default Clock Source
Asynchronous Timer Clock – clk
ADC Clock – clk
The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller
to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated
clock domain allows using this Timer/Counter as a real-time counter even when the device is in
sleep mode. It also allows the LCD controller output to continue while the rest of the device is in
sleep mode.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 8-1.
Note:
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before com-
mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the
start-up time. The number of WDT Oscillator cycles used for each time-out is shown in
2. The frequency of the Watchdog Oscillator is voltage dependent as shown in
teristics” on page
Table 8-2.
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is the Internal RC Oscillator with longest start-up time and an initial system
clock prescaling of 8. This default setting ensures that all users can make their desired clock
source setting using an In-System or Parallel programmer.
ADC
Device Clocking Option
External Crystal/Ceramic Resonator
External Low-frequency Crystal
Calibrated Internal RC Oscillator
External Clock
Reserved
Typ Time-out (V
1. For all fuses “1” means unprogrammed while “0” means programmed.
4.1ms
65ms
Device Clocking Options Select
Number of Watchdog Oscillator Cycles
342.
ASY
CC
= 5.0V)
Typ Time-out (V
(1)
4.3ms
69ms
CC
= 3.0V)
ATmega329P/3290P
0011, 0001, 0101, 0100
1111 - 1000
0111 - 0110
CKSEL3..0
0010
0000
Number of Cycles
64K (65,536)
4K (4,096)
”Typical Charac-
Table 8-
28

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