ATmega3290P Atmel Corporation, ATmega3290P Datasheet - Page 289

• Manufacturer Part Number: ATmega3290P
• Manufacturer: Atmel Corporation

Specifications of ATmega3290P

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.8.7
26.8.8
26.8.9
8021G–AVR–03/11
Setting the Boot Loader Lock Bits by SPM
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
RWWSB by writing the RWWSRE. See
page 291
To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write
“X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
See
Flash access.
If bits 5...0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM
instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-
pointer is don’t care during this operation, but for future compatibility it is recommended to load
the Z-pointer with 0x0001 (same as used for reading the Lock bits). For future compatibility it is
also recommended to set bits 7, and 6 in R0 to “1” when writing the Lock bits. When program-
ming the Lock bits the entire Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc-
tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR,
the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN
bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-
SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the
BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be
loaded in the destination register as shown below. Refer to
detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,
the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.
Refer to
Bit
R0
Bit
Rd
Bit
Rd
Table 26-2
Table 27-4 on page 298
for an example.
FLB7
and
7
7
1
7
–
Table 26-3
FLB6
6
6
1
6
–
for how the different settings of the Boot Loader bits affect the
for detailed description and mapping of the Fuse High byte.
BLB12
BLB12
FLB5
5
5
5
”Simple Assembly Code Example for a Boot Loader” on
BLB11
BLB11
FLB4
4
4
4
BLB02
BLB02
FLB3
3
3
3
ATmega329P/3290P
BLB01
BLB01
FLB2
2
2
2
Table 27-5 on page 298
FLB1
LB2
LB2
1
1
1
FLB0
LB1
LB1
0
0
0
for a
289