ATmega3290P Atmel Corporation, ATmega3290P Datasheet - Page 80

• Manufacturer Part Number: ATmega3290P
• Manufacturer: Atmel Corporation

Specifications of ATmega3290P

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.3.6
8021G–AVR–03/11
Alternate Functions of Port F
Table 13-17. Overriding Signals for Alternate Functions in PE3:PE0
Note:
The Port F has an alternate function as analog input for the ADC as shown in
some Port F pins are configured as outputs, it is essential that these do not switch when a con-
version is in progress. This might corrupt the result of the conversion. If the JTAG interface is
enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even
if a reset occurs.
Table 13-18. Port F Pins Alternate Functions
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg-
ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Port Pin
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
1. AIN0D and AIN1D is described in
PE3/AIN1/
PCINT3
0
0
0
0
0
0
–
(PCINT3 • PCIE0)
+ AIN1D
PCINT3 • PCIE0
PCINT3 INPUT
AIN1 INPUT
Alternate Function
ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)
ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)
ADC3 (ADC input channel 3)
ADC2 (ADC input channel 2)
ADC1 (ADC input channel 1)
ADC0 (ADC input channel 0)
(1)
PE2/XCK/AIN0/
PCINT2
XCK OUTPUT
ENABLE
XCK
0
0
0
0
–
(PCINT2 • PCIE0)
+ AIN0D
PCINT2 • PCIE0
XCK/PCINT2
INPUT
AIN0 INPUT
”DIDR1 – Digital Input Disable Register 1” on page
(1)
.
PE1/TXD/
PCINT1
TXEN
0
TXEN
1
TXEN
TXD
–
PCINT1 • PCIE0
1
PCINT1 INPUT
–
ATmega329P/3290P
PE0/RXD/
PCINT0
RXEN
PORTE0 • PUD
RXEN
0
0
0
–
PCINT0 • PCIE0
1
RXD/PCINT0
INPUT
–
Table
13-18. If
212.
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