ATmega329P Atmel Corporation, ATmega329P Datasheet

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... Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – Segment LCD Driver (ATmega329P) – Segment LCD Driver (ATmega3290P) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – ...

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... Pin Configurations Figure 1-1. MLF/ Pinout ATmega329P LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 14 (OC1A/PCINT13) PB5 15 (OC1B/PCINT14) PB6 16 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be sol- dered or glued to the board to ensure good mechanical stability ...

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... DNC 18 DNC 19 (SS/PCINT8) PB0 20 (SCK/PCINT9) PB1 21 (MOSI/PCINT10) PB2 22 (MISO/PCINT11) PB3 23 (OC0A/PCINT12) PB4 24 (OC1A/PCINT13) PB5 25 (OC1B/PCINT14) PB6 8021G–AVR–03/11 INDEX CORNER ATmega329P/3290P 75 PA3 (COM3) 74 PA4 (SEG0) 73 PA5 (SEG1) 72 PA6 (SEG2) 71 PA7 (SEG3) 70 PG2 (SEG4) 69 PC7 (SEG5) 68 PC6 (SEG6) 67 DNC 66 PH3 (PCINT19/SEG7) ...

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... Overview The ATmega329P/3290P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega329P/3290P achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

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... Self-Programmable Flash on a monolithic chip, the Atmel ATmega329P/3290P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded con- trol applications. The ATmega329P/3290P AVR is supported with a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...

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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega329P/3290P as listed on page 8021G– ...

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... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega329P/3290P as listed on page 2 ...

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... Shorter pulses are not guaranteed to generate a reset. , even if the ADC is not used. If the ADC is used, it should be connected large capacitance reduces ripple on V LCD reaches its target value. LCD ATmega329P/3290P ”System and Reset but increases LCD CC Fig- 8 ...

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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 8021G–AVR–03/11 1. ATmega329P/3290P 9 ...

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... AVR core architecture in general. The main function of the Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega329P/3290P Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog Timer ...

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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega329P/3290P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...

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... The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8021G–AVR–03/11 ® ® AVR Status Register – SREG – is defined as R/W R/W R/W R ⊕ V ATmega329P/3290P SREG R/W R/W R/W R ...

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... R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a data memory address, mapping them ATmega329P/3290P ® ® AVR Enhanced RISC instruction set. In order to 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 ...

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... Data is pushed onto the stack Return address is pushed onto the stack with a subroutine call or Decremented by 2 interrupt Incremented by 1 Data is popped from the stack Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt ATmega329P/3290P Figure 6- R26 (0x1A ...

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... The Parallel Instruction Fetches and Instruction Executions T1 clk CPU 1st Instruction Fetch 2nd Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU ATmega329P/3290P SP12 SP11 SP10 SP9 ...

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... Total Execution Time Result Write Back ® ® AVR provides several different interrupt sources. These interrupts and the separate for details. ”Boot Loader Support – Read-While-Write Self-Programming” on page ATmega329P/3290P ”Memory Pro- ”Interrupts” on page 53. The list also ”Interrupts” on page 53 for more information ...

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... Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8021G–AVR–03/11 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ; set Global Interrupt Enable ATmega329P/3290P 17 ...

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... The ATmega329P/3290P contains 132Kbytes On-chip In-System Reprogrammable Flash mem- ory for program storage. Since all AVR instructions are bits wide, the Flash is organized as 16K x 16 (ATmega329P/3290P). For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. ...

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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2,048bytes of internal data SRAM in the ATmega329P/3290P are all accessible through all these addressing modes. The Register File is described in page 13 ...

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... Figure 7-3. 7.4 EEPROM Data Memory The ATmega329P/3290P contains 1Kbytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

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... I/O Memory The I/O space definition of the ATmega329P/3290P is shown in 403. All ATmega329P/3290P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...

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... When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 7.6.2 EEARH and EEARL – EEPROM Address Register ATmega329P/3290P Bit 0x22 (0x42) 0x21 (0x41) ...

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... When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. 8021G–AVR–03/ – – – – ATmega329P/3290P EERIE EEMWE EEWE EERE R/W R/W R/W R ”Boot Loader for details about Boot ...

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... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 8021G–AVR–03/11 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 27,072 ATmega329P/3290P Table 7-1 lists the typical pro- Typical Programming Time 3.4ms 24 ...

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... EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega329P/3290P 25 ...

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... Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR MSB R/W R/W R MSB R/W R/W R MSB R/W R/W R ATmega329P/3290P R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R ...

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... Timer/Counter Modules clk I/O clk ASY Timer/Counter External Clock Oscillator is halted, enabling USI start condition detection in all sleep modes. I/O ATmega329P/3290P ® ® AVR and their distribution. All of 37. The clock systems are detailed below. CPU Core RAM clk AVR Clock CPU Control Unit ...

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... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 342. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out (V CC 4.1ms 65ms ATmega329P/3290P (1) CKSEL3..0 1111 - 1000 0111 - 0110 0010 0000 0011, 0001, 0101, 0100 ”Typical Charac- = 3.0V) ...

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... Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and SUT1..0 Power-save (1) 00 258 CK (1) 01 258 CK ( ATmega329P/3290P Figure 8-2. Either a quartz crystal or a XTAL2 XTAL1 GND Table 8-3. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...

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... The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega329P/3290P oscillator is optimized for very low power consumption, and thus when selecting crystals, see 12.5pF crystals. ...

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... Start-up Time from Power-down and Power-save ( 32K CK 1. This option should only be used if frequency stability at start-up is not important for the application 32. If selected, it will operate with no external components. During reset, Table 28-4 on page 335. ATmega329P/3290P ⋅ – Figure 8-2 on page 29 Figure 8-2 on page 29 ...

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... The device is shipped with this option selected 32. To run the device on an external clock, the CKSEL Fuses must be programmed External Clock Drive Configuration NC EXTERNAL CLOCK SIGNAL 33. Crystal Oscillator Clock Frequency ATmega329P/3290P 299. (1)(3) CKSEL3...0 0010 ), the CKDIV8 CC Additional Delay from Reset (V = 5.0V) ...

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... System Clock Prescaler The ATmega329P/3290P system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...

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... From the time the CLKPS values are written, it takes between and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here the previous clock period, and T2 is the period corresponding to the new prescaler setting. 8021G–AVR–03/11 ATmega329P/3290P 34 ...

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... R/W Device Specific Calibration Value Table 28-4 on page 335. The application software can write this register to change 335. Calibration outside that range is not guaranteed CLKPCE – – R 36. ATmega329P/3290P CAL3 CAL2 CAL1 R/W R/W R – CLKPS3 CLKPS2 CLKPS1 ...

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... ATmega329P/3290P CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 36 ...

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... SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 8021G–AVR–03/11 for more details. presents the different clock systems in the ATmega329P/3290P, and Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains X ...

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... CC 42. Writing this bit to one turns off the BOD in rele- 42. and clk , while allowing the other clocks to run. CPU FLASH ATmega329P/3290P Table 27-3 on page Table 9-1 on page ”MCUCR – , clk , and clk , while allowing the I/O CPU ...

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... PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. Module shutdown can be used in IDLE 8021G–AVR–03/11 ATmega329P/3290P ”External Interrupts” on page 58 ”Clock Sources” on page 28. ...

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... Comparator” on page 210 for details on the start-up time. ”Watchdog Timer” on page 48 for details on how to configure the Watchdog Timer. ATmega329P/3290P ”Analog to Digital Converter” on page 213 for details on how to configure the Analog ”Brown-out Detection” on page 47 ”Internal Volt- ...

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... Input Enable and Sleep Modes” on page 67 /2, the input buffer will use excessive power input pin can cause significant current even in active mode. Digital CC ”DIDR1 – Digital Input Disable Register 1” on page 212 for details. ATmega329P/3290P for details on and ”DIDR0 – Digital 41 ...

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... Standby mode is only recommended for use with external crystals or resonators JTD BODS BODSE R/W R/W R 37. Writing to the BODS bit is controlled by a timed sequence and an enable bit, ATmega329P/3290P – SM2 SM1 SM0 R R/W R/W R Table 9-2. Sleep Mode ...

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... Note: 8021G–AVR–03/ – – – PRLCD R The Analog Comparator is disabled using the ACD-bit in the and Status Register” on page 211. ATmega329P/3290P PRTIM1 PRSPI PRUSART0 R/W R/W R ”ACSR – Analog Comparator Control 0 PRADC PRR ...

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... Reset Sources The ATmega329P/3290P has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...

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... Watchdog Oscillator Clock Generator CKSEL[3:0] SUT[1:0] ”System and Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level. CC ATmega329P/3290P DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT 336. The POR is activated whenever 45 ...

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... Figure 10-4. External Reset During Operation 8021G–AVR–03/11 V POT RST RESET t TOUT RESET V POT V CC RESET RESET ”System and Reset Characteristics” on page CC ATmega329P/3290P CC V RST t TOUT 336) will generate a – on its positive edge, the RST – has expired. TOUT 46 ...

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... Brown-out Detection ATmega329P/3290P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...

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... Internal Voltage Reference ATmega329P/3290P features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...

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... WDE must be written to one to start the timed sequence. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 8021G–AVR–03/11 ATmega329P/3290P WATCHDOG OSCILLATOR 49 ...

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... Initial Value • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega329P/3290P and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

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... ATmega329P/3290P Typical Time-out at Typical Time-out 3. 5. 17.1ms 16.3ms 34.3ms 32.5ms 68.5ms 65ms 0.14s 0.13s 0.27s 0.26s 0.55s 0.52 1.1s 1 ...

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... WDTCR ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret (1) /* Reset WDT */ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; 1. See Section “5.” on page 9. ATmega329P/3290P 52 ...

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... Interrupts 11.1 Overview This section describes the specifics of the interrupt handling as performed in Atmel ATmega329P/3290P. For a general explanation of the AVR interrupt handling, refer to and Interrupt Handling” on page 11.2 Interrupt Vectors Table 11-1. Vector No ...

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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega329P/3290P is: Address 0x0000 0x0002 0x0004 0x0006 ...

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... Set Stack Pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx jmp RESET jmp EXT_INT0 ATmega329P/3290P ; Enable interrupts Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler ...

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... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 281 ATmega329P/3290P ; PCINT0 Handler ; ; Store Program Memory Ready Handler ...

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... MCUCR, r17 ret /* Enable change of Interrupt Vectors */ MCUCR |= (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR |= (1<<IVSEL JTD BODS BODSE R/W R/W R for details. ATmega329P/3290P PUD – – IVSEL R R ”Boot Loader Support – Read-While-Write 0 IVCE ...

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... Clock and Clock Options” on page Notes: 8021G–AVR–03/11 ”EICRA – External Interrupt Control Register A” on page 1. PCMSK3 and PCMSK2 are only present in ATmega3290P. 2. PCINT30:16 are only present in ATmega3290P. Only PCINT15:0 are present in ATmega329P. See ”Pin Configurations” on page 2 ATmega329P/3290P (1) ...

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... LE clk PCINT(0) in PCMSK(x) clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF – – – Table 12-1 on page ATmega329P/3290P Figure 12-1. pcint_in_(0) 0 pcint_syn pcint_setflag x clk – – – ISC01 R 60. The value on the INT0 pin is sampled before ...

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... The rising edge of INT0 generates an interrupt request (1) (1) PCIE3 PCIE2 PCIE1 R/W R/W R This bit is a reserved bit in ATmega329P and should always be written to zero. 1. This bit is a reserved bit in ATmega329P and should always be written to zero. ATmega329P/3290P PCIE0 – – – R ...

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... INT0 is configured as a level interrupt. 8021G–AVR–03/ (1) (1) PCIF3 PCIF2 PCIF1 R/W R/W R This bit is reserved bit in ATmega329P and will always be read as zero. 1. This bit is reserved bit in ATmega329P and will always be read as zero. ATmega329P/3290P PCIF0 – – – R ...

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... R/W R PCMSK3 and PCMSK2 are only present in ATmega3290P PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATmega329P/3290P PCINT27 PCINT26 PCINT25 R/W R/W R/W R PCINT19 PCINT18 PCINT17 R/W R/W R/W R PCINT11 ...

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... Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in 8021G–AVR–03/11 Figure 13-1. Refer to Pxn C pin ”Register Description” on page ATmega329P/3290P ”Electrical Characteristics” on page 330 R pu Logic See Figure "General Digital I/O" for Details 90. ...

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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 90, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega329P/3290P Figure 13-2 PUD Q D DDxn Q ...

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... Input 1 1 Input 0 X Output 1 X Output Figure 13-2, the PINxn Register bit and the preceding latch con- pd,max ATmega329P/3290P Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 13-3 shows a timing dia- and t respectively ...

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... SYNC LATCH PINxn r17 Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega329P/3290P XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx 0x00 ...

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... Figure 13-2, the digital input signal can be clamped to ground at the input of the ”Alternate Port Functions” on page ATmega329P/3290P /2. CC 69. 67 ...

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... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. 8021G–AVR–03/11 or GND is not recommended, since this may cause excessive currents if the pin is CC ATmega329P/3290P 68 ...

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... SLEEP, and PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ATmega329P/3290P Figure 13-2 can be overridden by ...

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... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. Some pins are connected to different LCD segments on ATmega329P and ATmega3290P. See pinout ”MLF/ Pinout ATmega329P” on page 2 8021G– ...

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... Overriding Signals for Alternate Functions in PA7:PA4 PA7/SEG3 PA6/SEG2 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – LCDSEG LCDSEG ATmega329P/3290P PA5/SEG1 PA4/SEG0 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – LCDSEG LCDSEG ...

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... Change Interrupt12). MISO/PCINT11 (SPI Bus Master Input/Slave Output or Pin Change Interrupt11). MOSI/PCINT10 (SPI Bus Master Output/Slave Input or Pin Change Interrupt10). SCK/PCINT9 (SPI Bus Serial Clock or Pin Change Interrupt9). SS/PCINT8 (SPI Slave Select input or Pin Change Interrupt8). ATmega329P/3290P PA1/COM1 PA0/COM0 LCDEN • LCDEN ...

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... PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt source. • SS/PCINT8 – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0 Slave, the SPI is activated when this pin is driven 8021G–AVR–03/11 ATmega329P/3290P 73 ...

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... SPI SLAVE SPI MSTR OUTPUT OUTPUT – – PCINT11 • PCIE1 PCINT10 • PCIE1 1 1 PCINT11 INPUT PCINT10 INPUT SPI MSTR INPUT SPI SLAVE INPUT – – ATmega329P/3290P PB5/OC1A/ PB4/OC0A/ PCINT13 PCINT12 OC1A ENABLE OC0A ENABLE OC1A OC0A – ...

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... Figure 13-5 on page 69. PC7/SEG5 PC6/SEG6 LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – LCDSEG LCDSEG ATmega329P/3290P PC5/SEG(11/7) PC4/SEG(12/8) LCDEN LCDEN 0 0 LCDEN LCDEN – – LCDEN LCDEN 0 0 – – LCDSEG LCDSEG 75 ...

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... SEG (LCD front plane 20/16) SEG (LCD front plane 21/17) SEG (LCD front plane 22/18) SEG (LCD front plane 23/19) SEG (LCD front plane 24/20) INT0/SEG (External Interrupt0 Input or LCD front plane 25/21) ICP1/SEG (Timer/Counter1 Input Capture pin or LCD front plane 26/22) ATmega329P/3290P PC1/SEG(15/11) PC0/SEG(16/12) LCDEN LCDEN 0 0 LCDEN ...

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... LCDEN • (LCDPM – – LCDEN • (LCDPM) LCDEN • (LCDPM – – LCDSEG LCDSEG ATmega329P/3290P PD5/SEG(21/17) PD4/SEG(22/18) LCDEN • (LCDPM) LCDEN • (LCDPM LCDEN • (LCDPM) LCDEN • (LCDPM – – LCDEN • (LCDPM) LCDEN • ...

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... USCK/SCL/PCINT4 (USART0 External Clock Input/Output or TWI Serial Clock or Pin Change Interrupt4) AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3) XCK/AIN0/ PCINT2 (USART0 External Clock or Analog Comparator Positive Input or Pin Change Interrupt2) TXD/PCINT1 (USART0 Transmit Pin or Pin Change Interrupt1) RXD/PCINT0 (USART0 Receive Pin or Pin Change Interrupt0) ATmega329P/3290P Table 13-15. 78 ...

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... WIRE clk DO I/O – – PCINT7 • PCIE0 PCINT6 • PCIE0 1 1 PCINT7 INPUT PCINT6 INPUT – – 1. CKOUT is one if the CKOUT Fuse is programmed ATmega329P/3290P PE5/DI/SDA/ PE4/USCK/SCL/ PCINT5 PCINT4 USI_TWO-WIRE USI_TWO-WIRE 0 0 USI_TWO-WIRE USI_TWO-WIRE (USI_SCL_HOLD (SDA + PORTE5) • + PORTE4) • DDE5 DDE4 USI_TWO-WIRE • ...

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... ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) ATmega329P/3290P PE1/TXD/ PCINT1 TXEN 0 TXEN 1 ...

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... JTAGEN JTAGEN 1 1 JTAGEN JTAGEN SHIFT_IR + 0 SHIFT_DR 0 JTAGEN 0 TDO – – JTAGEN JTAGEN 0 0 – – TDI ADC6 INPUT ADC7 INPUT ATmega329P/3290P PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN 1 1 JTAGEN JTAGEN – – JTAGEN JTAGEN 0 0 – – TMS TCK ...

Page 82

... T0/SEG (Timer/Counter0 Clock Input or LCD Front Plane 32/23) T1/SEG (Timer/Counter1 Clock Input or LCD Front Plane 33/24) SEG (LCD Front Plane 4/4) SEG (LCD Front Plane 17/13) SEG (LCD Front Plane 18/14) 1. Port G, PG5 is input only. Pull-up is always on. See Table 27-3 on page 297 for RSTDISBL fuse. ATmega329P/3290P PF1/ADC1 PF0/ADC0 ...

Page 83

... PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO AIO 8021G–AVR–03/11 and Table 13-22 relates the alternate functions of Port G to the overriding signals Figure 13-5 on page 69. ATmega329P/3290P PG4/T0/ SEG(32/23) LCDEN 0 LCDEN – LCDEN • (LCDPM INPUT – LCDSEG 83 ...

Page 84

... PCINT21/SEG (Pin Change Interrupt21 or LCD Front Plane 38) PCINT20/SEG (Pin Change Interrupt20 or LCD Front Plane 39) PCINT19/SEG (Pin Change Interrupt19 or LCD Front Plane 7) PCINT18/SEG (Pin Change Interrupt18 or LCD Front Plane 8) PCINT17/SEG (Pin Change Interrupt17 or LCD Front Plane 9) PCINT16/SEG (Pin Change Interrupt16 or LCD Front Plane 10) ATmega329P/3290P PG1/SEG(17/13) PG0/SEG(1814) LCDEN LCDEN 0 ...

Page 85

... PCINT17, Pin Change Interrupt Source 17: The P1 pin can serve as an external interrupt source. SEG, LCD front plane 9. • PCINT16/SEG – Port H, Bit 0 PCINT16, Pin Change Interrupt Source 16: The PH0 pin can serve as an external interrupt source. SEG, LCD front plane 10. 8021G–AVR–03/11 ATmega329P/3290P 85 ...

Page 86

... Table 13-25. Overriding Signals for Alternate Functions in PH7:4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO AIO Table 13-26. Overriding Signals for Alternate Functions in PH3:0 (ATmega329P/3290P) Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8021G–AVR–03/11 ...

Page 87

... PCINT29/SEG (Pin Change Interrupt29 or LCD Front Plane 28) PCINT28/SEG (Pin Change Interrupt28 or LCD Front Plane 29) PCINT27/SEG (Pin Change Interrupt27 or LCD Front Plane 30) PCINT26/SEG(Pin Change Interrupt26 or LCD Front Plane 31) PCINT25/SEG(Pin Change Interrupt25 or LCD Front Plane 34) PCINT24/SEG (Pin Change Interrupt26 or LCD Front Plane 35) ATmega329P/3290P 87 ...

Page 88

... PCINT24/SEG – Port J, Bit 0 PCINT24, Pin Change Interrupt Source 24: The PE24 pin can serve as an external interrupt source. SEG, LCD front plane 35. Table 13-28 on page 88 the overriding signals shown in Table 13-28. Overriding Signals for Alternate Functions in PJ7:4 (ATmega329P/3290P) Signal Name PUOE PUOV DDOE DDOV ...

Page 89

... Table 13-29. Overriding Signals for Alternate Functions in PH3:0 (ATmega329P/3290P) Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8021G–AVR–03/11 PJ3/PCINT27/ PJ2/PCINT26/ SEG30 SEG31 LCDEN LCDEN 0 0 LCDEN LCDEN – – PCINT27 • PCIE0 PCINT26 • PCIE0 • ...

Page 90

... PORTB4 R/W R/W R/W R DDB7 DDB6 DDB5 DDB4 R/W R/W R/W R PINB7 PINB6 PINB5 PINB4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega329P/3290P – – IVSEL IVCE R R R/W R PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 ...

Page 91

... PIND5 PIND4 R/W R/W R/W R/W N/A N/A N/A N PORTE7 PORTE6 PORTE5 PORTE4 R/W R/W R/W R DDE7 DDE6 DDE5 DDE4 R/W R/W R/W R ATmega329P/3290P PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 R/W ...

Page 92

... – – PING5 PING4 R N/A ( PORTH7 PORTH6 PORTH5 PORTH4 R/W R/W R/W R ATmega329P/3290P PINE3 PINE2 PINE1 PINE0 R/W R/W R/W R/W N/A N/A N/A N PORTF3 PORTF2 PORTF1 PORTF0 R/W R/W R/W R DDF3 DDF2 DDF1 DDF0 ...

Page 93

... PORTJ6 PORTJ5 R R – DDJ6 DDJ5 R R – PINJ6 PINJ5 R R/W R/W 0 N/A N/A 1. Register only available in ATmega3290P. ATmega329P/3290P DDH4 DDH3 DDH2 DDH1 R/W R/W R/W R PINH4 PINH3 PINH2 PINH1 R/W R/W R/W R/W N/A N/A N/A N PORTJ4 ...

Page 94

... The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk 8021G–AVR–03/11 ”MLF/ Pinout ATmega329P” on page 2 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The TCCRn ...

Page 95

... DATA BUS count clear TCNTn Control Logic direction bottom Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). ATmega329P/3290P ”System Clock Pres- TOVn (Int.Req.) Clock Select Edge Detector clk Tn ( From Prescaler ) top ”Output ...

Page 96

... Timer/Counter clock, referred to as clk Tn Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 99. ATmega329P/3290P in the following ...

Page 97

... CPU has access to the OCR0A Buffer Register, and if double buffering is disabled the CPU will access the OCR0A directly. 8021G–AVR–03/11 ”Modes of Operation” on page shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega329P/3290P 99). TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 97 ...

Page 98

... PORT) that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin System Reset occur, the OC0A Register is reset to “0”. 8021G–AVR–03/11 ATmega329P/3290P Figure 14-4 shows a sim- 98 ...

Page 99

... COMnx1 Waveform COMnx0 Generator FOCn clk I/O ”Register Description” on page Table 17-3 on page 156, and for phase correct PWM refer to ”Compare Match Output Unit” on page Figure 104. ATmega329P/3290P OCnx PORT D Q DDR 155. 156. For fast PWM mode, refer to Table 17-5 on page 156 ...

Page 100

... Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for 8021G–AVR–03/11 Figure ATmega329P/3290P 14-5. The counter value (TCNT0) OCnx Interrupt Flag Set (COMnx1 100 ...

Page 101

... OCnx Figure 14-6. The TCNT0 value is in the timing diagram shown as a his ATmega329P/3290P ) OCRnx OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 OC0 101 ...

Page 102

... The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. 8021G–AVR–03/11 ATmega329P/3290P Table 17-4 on page f clk_I/O ...

Page 103

... Compare Match. The point of this transition is to guarantee symmetry around BOT- TOM. There are two cases that give a transition without Compare Match. • OCR0A changes its value from MAX, like in OCn pin value is the same as the result of a down-counting Compare Match. To ensure 8021G–AVR–03/11 ATmega329P/3290P ...

Page 104

... I/O MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF0A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 ATmega329P/3290P ) is therefore shown MAX BOTTOM /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value BOTTOM + 1 BOTTOM + 1 /8) clk_I/O ...

Page 105

... Figure 4. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f /8) clk_I/O clk clk (clk TCNTn (CTC) OCRnx OCFnx 8021G–AVR–03/11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. I/O Tn /8) I/O TOP - 1 ATmega329P/3290P TOP BOTTOM TOP BOTTOM + 1 105 ...

Page 106

... The device-specific I/O Register and bit locations are listed in the Description” on page The PRTIM1 bit in Timer/Counter1 module. 8021G–AVR–03/11 ”MLF/ Pinout ATmega329P” on page 2 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are 127. ”Power Reduction Register” on page 39 ATmega329P/3290P Figure 15-1 ...

Page 107

... PWM or variable frequency output on the Output Compare pin (OC1A/B). See 8021G–AVR–03/11 Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1-2 on page 3, Timer/Counter1 pin placement and description. ATmega329P/3290P (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...

Page 108

... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation. ATmega329P/3290P 108 ...

Page 109

... Therefore, when both 8021G–AVR–03/11 (1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1; ... 1. See ”About Code Examples” on page 9 ATmega329P/3290P 109 ...

Page 110

... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See ”About Code Examples” on page 9 ATmega329P/3290P 110 ...

Page 111

... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See ”About Code Examples” on page 9 ”System Clock Prescaler” on page ATmega329P/3290P 33. 111 ...

Page 112

... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ”Modes of Operation” on page ATmega329P/3290P TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 118 ...

Page 113

... ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- 8021G–AVR–03/11 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn ATmega329P/3290P Figure 15-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...

Page 114

... Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be 8021G–AVR–03/11 109. ATmega329P/3290P ”Accessing 16-bit Registers” (Figure 16-1 on page 134). The edge detector is also ...

Page 115

... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega329P/3290P 118.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...

Page 116

... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 8021G–AVR–03/11 109. ATmega329P/3290P ”Accessing 16-bit Registers” 116 ...

Page 117

... Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the 8021G–AVR–03/11 Waveform Generator I/O ”Register Description” on page 127 ATmega329P/3290P Figure 15 OCnx 0 D ...

Page 118

... OCR1A or ICR1, and then counter (TCNT1) is cleared. 8021G–AVR–03/11 Table 15-2 on page ”Compare Match Output Unit” on page ”Timer/Counter Timing Diagrams” on page ATmega329P/3290P 127. For fast PWM mode refer to 117) Figure 15-6. The counter value (TCNT1) Table 15-3 on Table 15-4 on 125 ...

Page 119

... OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - ⋅ OCnA 2 N ATmega329P/3290P OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 119 ...

Page 120

... The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location 8021G–AVR–03/11 ( log TOP R = ---------------------------------- - FPWM log ATmega329P/3290P ) Figure 15-7. The figure OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...

Page 121

... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 8021G–AVR–03/11 ATmega329P/3290P Table 15-3 on page f clk_I/O f ...

Page 122

... Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg- 8021G–AVR–03/11 ATmega329P/3290P ( ) log + ...

Page 123

... ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: 8021G–AVR–03/11 f OCnxPCPWM 15-9). ATmega329P/3290P Table 1 on page f clk_I/O = --------------------------- - ⋅ ⋅ ...

Page 124

... R = ---------------------------------- - PFCPWM Figure 15-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega329P/3290P ( ) + 1 TOP log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...

Page 125

... OCnxPFCPWM Figure 15-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. ATmega329P/3290P f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value Table 1 on ...

Page 126

... FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. ATmega329P/3290P OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 ...

Page 127

... TOP COM1A1 COM1A0 COM1B1 R/W R/W R Table 15-2 Compare Output Mode, non-PWM COM1A0/COM1B0 ATmega329P/3290P /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 – – WGM11 R R shows the COM1x1:0 bit functionality when the Description Normal port operation, OC1A/OC1B disconnected ...

Page 128

... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See ”Phase Correct PWM Mode” on page 121 Table 15-5 on page ATmega329P/3290P (1) Description Normal port operation, OC1A/OC1B disconnected. WGM13 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected ...

Page 129

... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – R/W R ATmega329P/3290P Update of TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICR1 BOTTOM OCR1A BOTTOM ICR1 ...

Page 130

... I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – R/W R ATmega329P/3290P – – – – Figure 0 – TCCR1C ...

Page 131

... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See Section “15.3” on page 109. ATmega329P/3290P R/W R/W R/W R See Section “15.3” R/W R/W R/W R R/W R/W R/W R TCNT1H TCNT1L ...

Page 132

... ICIE1 (See Section “11.” on page 53.) is executed when the ICF1 Flag, located in TIFR1, is set. (See Section “11.” on page (See Section “11.” on page 53.) is executed when the TOV1 Flag, located in TIFR1, is set. ATmega329P/3290P ICR1[15:8] ICR1[7:0] R/W R/W R/W R/W 0 ...

Page 133

... TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 8021G–AVR–03/ – – ICF1 – R ATmega329P/3290P – OCF1B OCF1A TOV1 R R/W R/W R Table 15-5 on page 129 for the TOV1 ...

Page 134

... Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk clk I/O Synchronization ATmega329P/3290P /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O Figure 16-1 ) ...

Page 135

... Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1 clk PSR10 T0 T1 Note: 8021G–AVR–03/11 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins ( ATmega329P/3290P (1) T1 T1/T0) is shown in Figure /2.5. clk_I/O clk T0 16-1. 135 ...

Page 136

... CTC 1 1 Fast PWM 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Table 16-2 on page 137 ATmega329P/3290P COM0A0 WGM01 CS02 ...

Page 137

... A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See page 121 for more details. ATmega329P/3290P (1) ”Fast PWM Mode” on (1) ”Phase Correct PWM Mode” on ...

Page 138

... I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R ATmega329P/3290P TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R TCNT0 R OCR0 ...

Page 139

... – – – – ATmega329P/3290P – – OCIE0A TOIE0 R R R/W R – – OCF0A TOV0 R R R/W R ...

Page 140

... TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 8021G–AVR–03/ TSM – – – R ATmega329P/3290P – – PSR2 PSR10 GTCCR R R R/W R 140 ...

Page 141

... The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter- rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register 8021G–AVR–03/11 ”MLF/ Pinout ATmega329P” on page 2 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The count ...

Page 142

... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The assignment is depen- dent on the mode of operation default equal to the MCU clock, clk T2 157. For details on clock sources and prescaler, see 154. ATmega329P/3290P ”Output . When the AS2 I/O ”ASSR 142 ...

Page 143

... Signalizes that TCNT2 has reached maximum value. Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 146. ATmega329P/3290P TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler clk ...

Page 144

... TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 8021G–AVR–03/11 146. shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega329P/3290P TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 144 ...

Page 145

... The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction 8021G–AVR–03/11 Waveform Generator clk I/O ATmega329P/3290P Figure 17 OCnx 0 D ...

Page 146

... Description” on page Table 17-3 on page 156, and for phase correct PWM refer to ”Compare Match Output Unit” on page ”Timer/Counter Timing Diagrams” on page ATmega329P/3290P 155. 156. For fast PWM mode, refer to Table 17-5 on page 156. 145. Table 17-4 150 ...

Page 147

... This high frequency makes the fast PWM mode well suited 8021G–AVR–03/11 Figure clk_I ------------------------------------------------- - ⋅ ⋅ ( OCnx OCRnx Flag is set in the same timer clock cycle that the TOV2 ATmega329P/3290P 17-5. The counter value (TCNT2) OCnx Interrupt Flag Set (COMnx1 OC2A ) = 147 ...

Page 148

... Figure 17-6. The TCNT2 value is in the timing diagram shown as a his clk_I ----------------- - OCnxPWM N 256 ATmega329P/3290P OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 Table 17-4 on page 156). The actual ⋅ 148 ...

Page 149

... Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. 8021G–AVR–03/11 ATmega329P/3290P = f /2 when OCR2A is set to zero. This fea- oc2 clk_I/O ...

Page 150

... Figure 17-7 contains timing data for basic Timer/Counter operation. The figure shows the clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn ATmega329P/3290P Table 17-5 on page f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low even though Figure 17-7. When the OCR2A value is MAX the should be replaced by ...

Page 151

... TCNTn MAX - 1 TOVn shows the setting of OCF2A in all modes except CTC mode. clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. ATmega329P/3290P /8) clk_I/O MAX BOTTOM BOTTOM + 1 OCRnx OCRnx + 1 OCRnx Value /8) clk_I/O OCRnx + 2 151 ...

Page 152

... TOSC1 cycle to be reset. If the time between wake-up and reentering sleep mode is less than one TOSC1 cycle, correct interrupt handling is not guaranteed. If the 8021G–AVR–03/11 caler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx ATmega329P/3290P TOP BOTTOM BOTTOM + 1 TOP 152 ...

Page 153

... Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 8021G–AVR–03/11 ) again becomes active, TCNT2 will read as the previous value (before entering sleep) ATmega329P/3290P 153 ...

Page 154

... T2S Clear AS2 PSR2 CS20 CS21 CS22 . By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S ATmega329P/3290P 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S /8, clk T2S T2S as well as 0 (stop) may be selected. ...

Page 155

... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega329P/3290P COM2A0 WGM21 CS22 CS21 R/W ...

Page 156

... A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See page 149 for more details. 157. ATmega329P/3290P (1) ”Fast PWM Mode” on (1) ”Phase Correct PWM Mode” on ...

Page 157

... OCR2A[7:0] R/W R/W R/W R – – – EXCLK R ATmega329P/3290P /(No prescaling) /8 (From prescaler) /32 (From prescaler) /64 (From prescaler) /128 (From prescaler) /256 (From prescaler) /1024 (From prescaler R/W R/W R/W R R/W R/W R/W R ...

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... Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. 8021G–AVR–03/ – – – – ATmega329P/3290P . When AS2 is I – – OCIE2A TOIE2 R R R/W R TIMSK2 ...

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... TSM – – – R for a description of the Timer/Counter Synchronization mode. ATmega329P/3290P – – OCF2A TOV2 R R R/W R – – PSR2 PSR10 R R R/W R ...

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... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega329P/3290P and peripheral devices or between several AVR devices. A simplified block diagram of the Serial Peripheral Interface is shown in The PRSPI bit in SPI module. Figure 18-1. SPI Block Diagram Note: 8021G– ...

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... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high period should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. 8021G–AVR–03/11 ATmega329P/3290P Figure 18-2 on page SHIFT ENABLE 161 ...

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... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See ”Alternate Functions of Port B” on page 72 direction of the user defined SPI pins. ATmega329P/3290P ”Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 162 ...

Page 163

... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See Section “5.” on page 9. ATmega329P/3290P 163 ...

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... SPI_SlaveReceive ; Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. See Section “5.” on page 9. ATmega329P/3290P 164 ...

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... Table 18-3 on page 167 SPI Modes Conditions 0 CPOL=0, CPHA=0 1 CPOL=0, CPHA=1 2 CPOL=1, CPHA=0 3 CPOL=1, CPHA=1 ATmega329P/3290P 166. Data bits are shifted out and latched in on and Table 18-4 on page Leading Edge Trailing eDge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) ...

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... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega329P/3290P Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 ...

Page 167

... Figure 18-3 and Figure 18-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 18-3 on page 166 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega329P/3290P CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and ...

Page 168

... SPI Data Register. • Bit 5...1 – Res: Reserved Bits These bits are reserved bits in the ATmega329P/3290P and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...

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... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8021G–AVR–03/ MSB R/W R/W R/W R ATmega329P/3290P LSB R/W R/W R/W R SPDR Undefined 169 ...

Page 170

... A simplified block diagram of the USART Transmitter is shown in I/O Registers and I/O pins are shown in bold. The Power Reduction USART bit, PRUSART0 must be written to zero to enable USART0 module. 8021G–AVR–03/11 ATmega329P/3290P Figure 19-1. CPU accessible ”PRR – Power Reduction Register” on page 170 ...

Page 171

... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1-2 on page 3, Figure on page 78 for USART pin placement. ATmega329P/3290P Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD CONTROL ...

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... XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 19-2 on page 173 8021G–AVR–03/11 ATmega329P/3290P Figure shows a block diagram of the clock generation logic. 19-1) if the Buffer Registers are ...

Page 173

... Input from XCK pin (internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and ATmega329P/3290P U2X / ...

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... The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRnH and UBRRnL Registers, (0-4095) 194. Figure 19-2 on page 173 depends on the stability of the system clock source therefore recommended to osc ATmega329P/3290P Equation for Calculating UBRRn (1) f OSC UBRRn ( ) ...

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... XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 19-4 shows, when UCPOLn is zero the data will be changed at illustrates the possible combinations of the frame formats. Bits inside brackets are (IDLE ATmega329P/3290P Sample Sample FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 175 ...

Page 176

... – even ⊕ odd n 1 – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n ATmega329P/3290P … ⊕ ⊕ ⊕ ⊕ ⊕ … ⊕ ⊕ ⊕ ...

Page 177

... UCSR0C,r16 ret (1) ... USART_Init(MYUBRR) ... /* Set baud rate */ UBRR0H = (unsigned char)(ubrr>>8); UBRR0L = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSR0B = (1<<RXEN0)|(1<<TXEN0); /* Set frame format: 8data, 2stop bit */ UCSR0C = (1<<USBS0)|(3<<UCSZ00); 1. See ”About Code Examples” on page 9 ATmega329P/3290P 177 ...

Page 178

... Wait for empty transmit buffer sbis UCSR0A,UDRE0 rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR0,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSR0A & (1<<UDRE0 Put data into buffer, sends the data */ UDR0 = data; 1. See Section “5.” on page 9. ATmega329P/3290P 178 ...

Page 179

... Put data into buffer, sends the data */ UDR0 = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB80 bit of the UCSRnB Register is used after initialization. 2. See Section “5.” on page 9. ATmega329P/3290P 179 ...

Page 180

... Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant 8021G–AVR–03/11 ATmega329P/3290P 180 ...

Page 181

... Wait for data to be received sbis UCSR0A, RXC0 rjmp USART_Receive ; Get and return received data from buffer in r16, UDR0 ret (1) /* Wait for data to be received */ while ( !(UCSR0A & (1<<RXC0 Get and return received data from buffer */ return UDR0; 1. See Section “5.” on page 9. ATmega329P/3290P 181 ...

Page 182

... Get status and 9th bit, then data */ /* from buffer */ status = UCSR0A; resh = UCSR0B; resl = UDRn error, return - status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See ”About Code Examples” on page 9 ATmega329P/3290P 182 ...

Page 183

... Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together 8021G–AVR–03/11 ”Parity Bit Calculation” on page 176 ATmega329P/3290P and ”Parity Checker” on page 183. ...

Page 184

... Note the 8021G–AVR–03/11 (1) sbis UCSR0A, RXC0 ret in r16, UDR0 rjmp USART_Flush (1) unsigned char dummy; while ( UCSR0A & (1<<RXC0) ) dummy = UDR0; 1. See ”About Code Examples” on page 9 ATmega329P/3290P Figure 19-6 184 ...

Page 185

... RxD Sample (U2X = Sample (U2X = shows the sampling of the stop bit and the earliest possible beginning of the start bit ATmega329P/3290P START Figure 19-7 shows the sampling of the data bits and ...

Page 186

... R is the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 19-2 list the maximum receiver baud rate error that can be tolerated. Note ATmega329P/3290P STOP 1 (A) ( ...

Page 187

... Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104,35 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega329P/3290P Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 ± 3.0 +5.79/-5.88 ± 2.5 +5.11/-5.19 ± 2.0 +4.58/-4.54 ± 2.0 +4.14/-4.19 ± 1.5 +3.78/-3.83 ± 1.5 Recommended Max Max Total Error (%) Receiver Error (%) +5.66/-5.88 ± 2.5 +4.92/-5.08 ± 2.0 +4.35/-4.48 ± 1.5 +3.90/-4.00 ± 1.5 +3.53/-3.61 ± ...

Page 188

... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 8021G–AVR–03/11 ATmega329P/3290P 188 ...

Page 189

... TXCIEn bit). 8021G–AVR–03/ RXBn[7:0] TXBn[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R ATmega329P/3290P R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDRn (Read) UDRn (Write) UCSRnA ...

Page 190

... RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in UCSRnA is set. 8021G–AVR–03/11 ”Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega329P/3290P 187 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 190 ...

Page 191

... Bit 6 – UMSELn: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Figure 19-9. UMSELn Bit Settings 8021G–AVR–03/ – UMSELn UPMn1 UPMn0 R R/W R/W R UMSELn Mode 0 Asynchronous Operation 1 Synchronous Operation ATmega329P/3290P USBSn UCSZn1 UCSZn0 R/W R/W R UCPOLn UCSRnC R/W 0 191 ...

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... USBSn 0 1 UCSZn2 UCSZn1 ATmega329P/3290P Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity Stop Bit(s) 1-bit 2-bit UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit ...

Page 193

... R/W R/W R 186). The error values are calculated using the following equation: BaudRate ⎛ Error[%] ------------------------------------------------------- - 1 = ⎝ ATmega329P/3290P Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge – UBRRn[11:8] UBRRn[7: R/W R/W R/W R/W R/W R/W ...

Page 194

... U2Xn = 1 U2Xn = 0 Error UBRRn Error 0.2% 47 0.0% 0.2% 23 0.0% 0.2% 11 0.0% -3.5% 7 0.0% -7.0% 5 0.0% 8.5% 3 0.0% 8.5% 2 0.0% 8.5% 1 0.0% -18.6% 1 -25.0% 8.5% 0 0.0% – – – – – – 125kbps 115.2kbps ATmega329P/3290P f = 2.0000MHz osc U2Xn = 1 U2Xn = 0 UBRRn Error UBRRn Error 95 0.0% 51 0.2% 47 0.0% 25 0.2% 23 0.0% 12 0.2% 15 0.0% 8 -3.5% 11 0.0% 6 -7.0% 7 0.0% 3 8.5% 5 0.0% 2 8.5% 3 0.0% 1 8.5% 2 0.0% 1 -18.6% 1 ...

Page 195

... ATmega329P/3290P f = 7.3728MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0.0% 63 0.2% 23 0.0% 47 2.1% 15 0.0% 31 0.2% 11 0.0% 23 -3.5% 7 0.0% 15 -7.0% 5 0.0% 11 8.5% 3 0.0% 7 8.5% 1 0. ...

Page 196

... U2Xn = 0 Error UBRRn Error UBRRn -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – – 0.0% – – 1Mbps 691.2kbps ATmega329P/3290P MHz f = 14.7456MHz osc U2Xn = 1 U2Xn = 0 Error UBRRn Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0.0% 95 0.0% 63 0.0% 71 0.0% 47 0.0% 47 0.0% 31 0.0% 35 0.0% 23 0.0% 23 0.0% 15 0.0% 17 0.0% 11 0.0% 11 0.0% 7 0. ...

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... U2Xn = 0 Error UBRRn Error UBRRn 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – – 0.0% – – 2Mbps 1.152Mbps ATmega329P/3290P f = 20.0000MHz osc U2Xn = 1 U2Xn = 0 Error UBRRn Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0.0% 86 -0.2% 119 0.0% 64 0.2% 79 0.0% 42 0.9% 59 0.0% 32 -1.4% 39 0.0% 21 -1.4% 29 0.0% 15 1.7% 19 0.0% 10 -1. ...

Page 198

... Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. 8021G–AVR–03/11 ”MLF/ Pinout ATmega329P” on page 2 . CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The 3 2 ...

Page 199

... USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. 8021G–AVR–03/11 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MASTER shows two USI units operating in Three-wire mode, one as Master and one as ATmega329P/3290P DO DI USCK DO DI USCK PORTxn 199 ...

Page 200

... (Figure 20-3), a bus transfer involves the following steps: sts USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC) sts USICR,r16 lds r16, USISR sbrs r16, USIOIF ATmega329P/3290P LSB LSB E 200 ...